ICS932S801AFLF Datasheet, PDF (14/20 Pages) List of Unclassifed Manufacturers – K8 Clock Chip for Serverworks GC-HT 2-Way Servers

ICS932S801
SMBus Table: CPU Frequency Control Register
Byte 11 Pin #
Name
Control Function Type
0
1
PWD
Bit 7
-
N Div8
N Divider Prog bit 8 RW The decimal representation X
Bit 6
-
N Div9
N Divider Prog bit 9 RW of M and N Divier in Byte X
Bit 5
-
M Div5
RW 11 and 12 will configure
X
Bit 4
-
M Div4
RW the CPU VCO frequency. X
Bit 3
-
Bit 2
-
Bit 1
-
M Div3
M Div2
M Div1
RW Default at power up = latch- X
M Divider Programming _{RW in or Byte 0 Rom table.}
X
bit (5:0)
RW VCO Frequency = 14.318 X
Bit 0
-
M Div0
x [NDiv(9:0)+8] /
RW
[MDiv(5:0)+2]
X
SMBus Table: CPU Frequency Control Register
Byte 12 Pin #
Name
Control Function
Bit 7
-
N Div7
Bit 6
-
N Div6
Bit 5
-
N Div5
Bit 4
-
N Div4
N Divider Programming
Bit 3
-
N Div3
Byte12 bit(7:0) and
Bit 2
-
N Div2
Byte11 bit(7:6)
Bit 1
-
N Div1
Bit 0
-
N Div0
Type
0
1
PWD
RW The decimal representation X
RW of M and N Divier in Byte X
RW 11 and 12 will configure
X
RW the CPU VCO frequency. X
RW Default at power up = latch- X
RW in or Byte 0 Rom table.
X
RW VCO Frequency = 14.318 X
x [NDiv(9:0)+8] /
RW
[MDiv(5:0)+2]
X
SMBus Table: CPU Spread Spectrum Control Register
Byte 13 Pin #
Name
Control Function
Bit 7
-
SSP7
Bit 6
-
SSP6
Bit 5
-
SSP5
Bit 4
-
SSP4
Spread Spectrum
Bit 3
-
SSP3
Programming bit(7:0)
Bit 2
-
SSP2
Bit 1
-
SSP1
Bit 0
-
SSP0
Type
0
1
RW
RW
RW These Spread Spectrum
RW bits in Byte 13 and 14 will
RW
program the spread
RW
pecentage of CPU
RW
RW
PWD
X
X
X
X
X
X
X
X
SMBus Table: CPU Spread Spectrum Control Register
Byte 14 Pin #
Name
Control Function
Bit 7
-
Reserved
Reserved
Bit 6
-
SSP14
Bit 5
-
SSP13
Bit 4
-
Bit 3
-
Bit 2
-
SSP12
SSP11
SSP10
Spread Spectrum
Programming bit(14:8)
Bit 1
-
SSP9
Bit 0
-
SSP8
Type
0
1
R
-
-
RW
RW _{These Spread Spectrum}
RW _{bits in Byte 13 and 14 will}
RW
RW
program the spread
pecentage of CPU
RW
RW
PWD
0
X
X
X
X
X
X
X
0959C—03/13/06
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