ICS932S801AFLF Datasheet, PDF (11/20 Pages) List of Unclassifed Manufacturers – K8 Clock Chip for Serverworks GC-HT 2-Way Servers

ICS932S801
SMBus Table: Frequency Select and Spread Control Register
Byte 0 Pin #
Name
Control Function Type
0
1
PWD
Bit 7
-
Latched Input or SMBus
Latched
FS Source
Frequency Select
RW
Inputs
SMBus
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
CPU SS_EN
SRC SS_EN
Reserved
FS3
FS2
FS1
FS0
Spread Enable for CPU
and SRC PLLs. Setting ^RW
OFF
ON
0
SPREAD_EN to '1',
forces Spread ON for _RW
both PLLs.
OFF
ON
0
Reserved
RW Reserved Reserved 0
Freq Select Bit 3 RW
0
Freq Select Bit 2
Freq Select Bit 1
RW See Functionality Table on Latched
RW
Page 1
Latched
Freq Select Bit 0 RW
Latched
SMBus Table: Output Control Register
Byte 1 Pin #
Name
Bit 7
PCICLK3
Bit 6
PCICLK2
Bit 5
PCICLK1
Bit 4
PCICLK0
Bit 3
HTTCLK3
Bit 2
HTTCLK2
Bit 1
HTTCLK1
Bit 0
HTTCLK0
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
0
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBus Table: Output Control Register
Byte 2 Pin #
Name
Bit 7
48MHz_1
Bit 6
48MHz_0
Bit 5
REF1
Bit 4
REF0
Bit 3
CPUCLK8(3)
Bit 2
CPUCLK8(2)
Bit 1
CPUCLK8(1)
Bit 0
CPUCLK8(0)
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
When Disabled
CPUCLKT = 0
CPUCLKC = 1
Type
0
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable
RW Disable
RW Disable
RW Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
0959C—03/13/06
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