RFM31B Datasheet, PDF (44/63 Pages) List of Unclassifed Manufacturers – ISM RECEIVER

RFM31B
8.7. Low Duty Cycle Mode
The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available.
The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid preamble or sync
word is not detected the chip will return to sleep mode until the beginning of a new WUT period. If a valid preamble
and sync are detected the receiver on period will be extended for the low duty cycle mode duration (TLDC) to
receive all of the packet. The WUT period must be set in conjunction with the low duty cycle mode duration. The R
value (Reg 14h) is shared between the WUT and the TLDC. The ldc[7:0] bits are located in “Register 19h. Low
Duty Cycle Mode Duration.” The time of the TLDC is determined by the formula below:
TLDC  ldc [ 7 : 0 ]  ^{4  2 R} ms
32 .768
Figure 22. Low Duty Cycle Mode
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