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RFM31B Datasheet, PDF (17/63 Pages) List of Unclassifed Manufacturers – ISM RECEIVER
RFM31B
3.3. Interrupts
The RFM31B is capable of generating an interrupt signal when certain events occur.The chip notifies the
microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal
will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown
below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers
03h–04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change
in status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable
Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller reads the
interrupt status register. If the interrupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the
status may still be read at anytime in the Interrupt Status registers.
Add R/W Function/Descript D7
D6
D5
D4 D3 D2
D1
D0 POR Def.
ion
03 R Interrupt Status 1 ifferr Reserved Reserved irxffafull iext Reserved ipkvalid icrcerror —
04 R Interrupt Status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor
—
05 R/W Interrupt Enable 1 enfferr Reserved Reserved enrxffafull enext Reserved enpkvalid encrcerror 00h
06 R/W Interrupt Enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor
01h
For a complete descriptions of each interrupt, see “RFM31B Register Descriptions.”
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