RFM31B Datasheet, PDF (12/63 Pages) List of Unclassifed Manufacturers – ISM RECEIVER

RFM31B
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The RFM31B communicates with the host MCU over a standard 3-wire SPI interface:SCLK, SDI,and nSEL. The
host MCU can read data from the device on the SDO output pin. A SPI transaction is a 16-bit sequence which
consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA)
as demonstrated in Figure 2. The 7-bit address field is used to select one of the 128, 8-bit control registers. The
R/W select bit determines whether the SPI transaction is a read or write transaction. If R/W = 1 it signifies a WRITE
transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the RFM31B
every eight clock cycles. The timing parameters for the SPI interface are shown in Table 9. The SCLK rate is
flexible with a maximum rate of 10 MHz.
SDI
SCLK
nSEL
MSB
Address
Data
LSB
RW A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 xx xx RW A7
Figure 2. SPI Timing
Table 9. Serial Interface Timing Parameters
Symbol
Parameter
Min (nsec)
t_CH
Clock high time
40
t_CL
Clock low time
40
t_DS
Data setup time
20
t_DH
Data hold time
20
t_DD Output data delay time
20
t_EN
Output enable time
20
t_DE
Output disable time
50
t_SS
Select setup time
20
t_SH
Select hold time
50
t_SW
Select high period
80
SCLK
tSS
SDI
SDO
tEN
nSEL
Diagram
tCL tCH tDS tDH tDD
tSH tDE
tSW
To read back data from the RFM31B,the R/W bit must be set to 0 followed by the 7-bit address of the register from
which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored n the SDI pin when R/W = 0. The next
eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read
from the selected register will be available on the SDO output pin. The READ function is shown in Figure 3. After
the READ function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the last
data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.
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