RFM31B Datasheet, PDF (28/63 Pages) List of Unclassifed Manufacturers – ISM RECEIVER

RFM31B
6. Data Handling and Packet Handler
The internal modem is designed to operate with a packet including a 10101... preamble structure. To configure the
modem to operate with packet formats without a preamble or other legacy packet structures contact customer
support.
6.1. RX FIFO
A 64 byte FIFO is integrated into the chip for RX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to
access the FIFO. A burst read, as described in "3.1. Serial Peripheral Interface (SPI)" , from address
7Fh will read data from the RX FIFO.
RX FIFO
RX FIFO Almost Full
Threshold
Figure 10. FIFO Threshold
Add R/W Function/D D7
D6
D5
escription
08 R/W Operating & antdiv[2] antdiv[1] antdiv[0]
Function
Control 2
D4
D3
D2
rxmpk Reserved enldm
D1
D0 POR Def.
ffclrrx Reserved 00h
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the
incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcontroller via the
nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.
Add R/W Function/De D7
D6
D5
D4
D3
D2
D1
D0
scription
7E R/W
RX FIFO
Control
Reserved Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0]
POR
Def.
37h
The RX FIFO may be cleared or reset with the ffclrrx bit in “Register 08h. Operating Mode and Function Control 2,”.
All interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1"
and “Register 06h. Interrupt Enable 2,”. If the interrupts are not enabled the function will not generate
an interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers.
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