SKY72310 Datasheet, PDF (4/19 Pages) List of Unclassifed Manufacturers – SKY72310: Spur-Free, 2.1 GHz Single Fractional-N Frequency Synthesizer

DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
LSB last while the CS signal is low. If the CS signal is low for
more than 16 clock cycles, only the last address or data bits are
used to load the registers.
Register Programming
Register programming equations, described in this section, use
the following variables and constants:
N_fractional
Desired VCO division ratio in fractional-N applications.
This is a real number and can be interpreted as the
reference frequency (F_ref) multiplying factor so that the
resulting frequency is equal to the desired VCO
frequency.
N_integer
Desired VCO division ratio in integer-N applications.
This number is an integer and can be interpreted as
the reference frequency (F_ref) multiplying factor so that
the resulting frequency is equal to the desired VCO
frequency.
N_reg
Nine-bit unsigned input value to the divider ranging
from 0 to 511 (integer-N mode) and from 6 to 505
(fractional-N mode).
divider
This constant equals 262144 when the ∆Σ modulator
is in 18-bit mode, and 1024 when the ∆Σ modulator is
in 10-bit mode.
dividend
When in 18-bit mode, this is the 18-bit signed input
value to the ∆Σ modulator, ranging from –131072 to
+131071 and providing 262144 steps, each step equal
to F_{div_ref}/2¹⁸ Hz.
When in 10-bit mode, this is the 10-bit signed input
value to the ∆Σ modulator, ranging from –512 to +511
and providing 1024 steps, each step equal to
Fdiv_ref/2¹⁰ Hz.
F_VCO
F_{div_ref}
Desired VCO frequency.
Divided reference frequency presented to the phase
detector.
Fractional-N Applications. The desired division ratio for the
synthesizer is given by:
N
fractional
=
F_VCO
F_{div _ ref}
where N_fractional must be between 37.5 and 537.5.
The value to be programmed in the Divider Register is given by:
N_reg = Round( N _fractional )− 32
NOTE: The Round function rounds the number to the nearest
integer.
When in fractional mode, allowed values for N_reg are from 6 to 505
inclusive.
The value to be programmed by either of the Dividend Registers
(MSB or LSB) is given by:
dividend = Round [ divider×( N _fractional − N_reg −32 )]
where the divider is either 1024 in 10-bit mode or 262144 in
18-bit mode. Therefore, the dividend is a signed binary value
either 10 or 18 bits long.
NOTE: Because of the high fractionality of the SKY72310, there is
no practical need for any integer relationship between the
reference frequency and the channel spacing or desired
VCO frequencies.
Sample calculations for two fractional-N applications are provided
in Figure 4.
Clock
Data
X A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX
CS
Last
C1413
Figure 3. Serial Transfer Timing Diagram
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
4
July 30, 2008 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200705E