SKY72310 Datasheet, PDF (3/19 Pages) List of Unclassifed Manufacturers – SKY72310: Spur-Free, 2.1 GHz Single Fractional-N Frequency Synthesizer

DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Technical Description
The SKY72310 is a fractional-N frequency synthesizer using a ∆Σ
modulation technique. The fractional-N implementation provides
low in-band noise by having a low division ratio and fast
frequency settling time. In addition, the SKY72310 provides
arbitrarily fine frequency resolution with a digital word, so that the
frequency synthesizer can be used to compensate for crystal
frequency drift in the RF transceiver.
Serial Interface
The serial interface is a versatile three-wire interface consisting of
three pin signals: Clock (serial clock), Data (serial input), and CS
(chip select). It enables the SKY72310 to operate in a system
where one or multiple masters and slaves are present. To perform
a loopback test at startup and to check the integrity of the board
and processor, the serial data is fed back to the master device
(e.g., a microcontroller or microprocessor unit) through a
programmable multiplexer. This facilitates hardware and software
debugging.
NOTE: The divided crystal oscillator frequency (the internal
reference frequency), Fref_main, is referred to as
“reference frequency” throughout this document.
Phase Detector and Charge Pump
The SKY72310 uses a charge pump phase detector that provides
a programmable gain, Kd, from 31.25 to 1000 µA/2π radians in
32 steps. The phase detector is programmed using the Phase
Detector/Charge Pump Control Register.
Frequency Steering
When programmed for frequency power steering, the SKY72310
has a circuit that helps the loop filter steer the VCO using the
LD/PSmain signal (pin 4). In this configuration, the LD/PSmain
signal can provide a more rapid acquisition.
When programmed for lock detection, internal frequency steering
is implemented and provides frequency acquisition times
comparable to conventional phase/frequency detectors.
∆Σ Modulator
The SKY72310 provides fractionality through the use of a
proprietary, configurable 10-bit or 18-bit ∆Σ modulator. The
output from the modulator is combined with the divider ratio
through its fractional units.
Lock Detection
When programmed for lock detection, the SKY72310 provides an
active low, pulsing open collector output using the LD/PSmain
signal (pin 4) to indicate the out-of-lock condition. When locked,
the LD/PSmain signal is tri-stated (high impedance).
VCO Prescaler
The VCO prescaler provides low-noise signal conditioning of the
VCO signal. It translates an off-chip, single-ended or differential
signal to an on-chip differential Current Mode Logic (CML) signal.
Power Down
The SKY72310 supports a number of power-down modes through
the serial interface. For more information, see the Register
Descriptions section of this document.
VCO Divider
The SKY72310 provides a programmable divider that controls the
CML prescaler and supplies the required signal to the charge
pump phase detector. Programmable divide ratios ranging from
38 to 537 are possible in fractional-N mode and from 32 to 543 in
integer-N mode.
Reference Frequency Oscillator
The SKY72310 has a self-contained, low-noise crystal oscillator.
This crystal oscillator is followed by the clock generation circuitry
that generates the required clock for the programmable reference
frequency divider.
Reference Frequency Divider
The crystal oscillator signal can be divided by a ratio of 1 to 32 to
create the reference frequency for the phase detector. The divide
ratio is programmed using the Reference Frequency Dividers
Register.
Serial Interface Operation
The serial interface consists of three pins: Clock (pin 22), Data
(pin 20), and CS (pin 21). The Clock signal controls data on the
two serial data lines (Data and CS). The Data pin shifts bits into a
temporary register on the rising edge of Clock. The CS signal
allows individual selection transfers that synchronize and sample
the information of slave devices on the same bus.
Figure 3 functionally depicts how a serial transfer takes place. A
serial transfer is initiated when a microcontroller or
microprocessor forces the CS signal to a low state. This is
followed immediately by an address/data stream sent to the Data
pin that coincides with the rising edges of the clock presented at
the Clock pin.
Each rising edge of the Clock signal shifts in one bit of data on the
Data line into a shift register. At the same time, one bit of data is
shifted out of the Mux_out pin (if the serial bit stream is selected)
at each falling edge of Clock. To load any of the registers, 16 bits
of address or data must be presented to the Data line with the
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200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
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