M0519 Datasheet, PDF (35/69 Pages) List of Unclassifed Manufacturers – 32-bit Microcontroller

M0519
6.3 Clock Controller
6.3.1 Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex^® -M0 core executes the WFI instruction only if the SLEEPDEEP
(SCR[2]) bit is set to 1. After that, chip enters Power-down mode and wait for wake-up interrupt
source triggered to leave Power-down mode. In the Power-down mode, the clock controller turns
off the 4~24 MHz external high speed crystal oscillator and 22.1184 MHz internal high speed RC
oscillator to reduce the overall system power consumption. Figure 6-3 shows the clock generator
and the overview of the clock source control.
The clock generator consists of 4 clock sources as listed below:
 4~24 MHz external high speed crystal oscillator (HXT)
 Programmable PLL output clock frequency (PLL_FOUT), PLL source can be selected
from 4~24 MHz external high speed crystal oscillator (HXT) or 22.1184 MHz internal
high speed RC oscillator (HIRC)
 22.1184 MHz internal high speed RC oscillator (HIRC)
 10 kHz internal low speed RC oscillator (LIRC)
Each of these clock sources has certain stable time to wait for clock operating at stable
frequency. When clock source is enabled, a stable counter start counting and correlated clock
stable
index
(OSC22M_STB(CLKSTATUS[4]),
OSC10K_STB(CLKSTATUS[3]),
PLL_STB(CLKSTATUS[2]) and XTL12M_STB(CLKSTATUS[0])) are set to 1 after stable counter
value reach a define value as Table 6-5. System and peripheral can use these clock as its
operating clock only when correlate clock stable index is set to 1. The clock stable index will auto
clear when user disables the clock source (OSC10K_EN(PWRCON[3]),
OSC22M_EN(PWRCON[2]), XTL12M_EN(PWRCON[0]) and PD(PLLCON[16])). Besides, the
clock stable index of HXT, HIRC and PLL will auto clear when chip enter power-down and clock
stable counter will re-counting after chip wake-up if correlate clock is enabled.
Clock Source
HXT
PLL
HIRC
LIRC
Clock Stable Count Value
4096 HXT clock
6144 PLL source
(PLL source is HXT if PLL_SRC(PLLCON[19]) = 0, or HIRC if PLL_SRC(PLLCON[19]) = 1)
256 HIRC clock
1 LIRC
Table 6-5 Clock Stable Count Value Table
Nov. 02, 2016
Page 35 of 69
Rev 1.02