M0519 Datasheet, PDF (26/69 Pages) List of Unclassifed Manufacturers – 32-bit Microcontroller

M0519
6.2 System Manager
6.2.1 Overview
System management includes the following sections:
 System Resets
 System Power Distribution
 System Memory Map
 System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
 System Timer (SysTick)
 Nested Vectored Interrupt Controller (NVIC)
 System Control registers
6.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
 Hardware Reset
 Power-on Reset (POR)
 Low level on the Reset pin (nRESET)
 Watchdog Time-out Reset (WDT)
 Low Voltage Reset (LVR)
 Brown-out Detector Reset (BOD)
 Software Reset
 SYS Reset - SYSRESETREQ (AIRCR[2])
 Cortex^® -M0 Core One-shot Reset - CPU_RST (IPRSTC1[1])
 Chip One-shot Reset - CHIP_RST (IPRSTC1[0])
Power-on Reset or CHIP_RST (IPRST1[0]) reset the whole chip including all peripherals,
external crystal circuit and BS (ISPCON[1]) bit.
SYSRESETREQ (AIRCR[2]) reset the whole chip including all peripherals, but does not reset
external crystal circuit and BS (ISPCON[1]) bit.
Nov. 02, 2016
Page 26 of 69
Rev 1.02