MC3433 Datasheet, PDF (25/45 Pages) List of Unclassifed Manufacturers – Axis Accelerometer

MC3433 3-Axis Accelerometer
Preliminary Datasheet
10.3 I2C MESSAGE FORMAT
Note that at least one I2C STOP condition must be present between samples in order for
the sensor to update the sample data registers.
The device uses the following general format for writing to the internal registers. The I2C
master generates a START condition, and then supplies the 7-bit device ID. The 8^th bit is the
R/W# flag (write cycle = 0). The device pulls SDA low during the 9^th clock cycle indicating a
positive ACK.
The second byte is the 8-bit register address of the device to access, and the last byte is the
data to write.
I2C Master
(To Sensor)
I2C Slave
(From Sensor)
START
Device ID
R/W#
Register Address
Register Data to Write
Stop
S
11011100
R7 R6 R5 R4 R3 R2 R1 R0
D7 D6 D5 D4 D4 D2 D1 D0
P
ACK
ACK/NAK
ACK
ACK/NAK
ACK
ACK/NAK
Figure 11. I2C Message Format, Write Cycle, Single Register Write
In a read cycle, the I2C master writes the device ID (R/W#=0) and register address to be read.
The master issues a RESTART condition and then writes the device ID with the R/W# flag set
to ‘1’. The device shifts out the contents of the register address.
I2C Master
(To Sensor)
START
Device ID
R/W#
S
11011100
Register Address
Restart
Device ID
R/W#
R7 R6 R5 R4 R3 R2 R1 R0
R
11011101
NAK
NAK
STOP
P
I2C Slave
(from Sensor)
ACK
ACK/NAK
ACK
ACK/NAK
ACK
ACK/NAK
D7 D6 D5 D4 D3 D2 D1 D0
Read Data Byte
Figure 12. I2C Message Format, Read Cycle, Single Register Read
The I2C master may write or read consecutive register addresses by writing or reading
additional bytes after the first access. The device will internally increment the register address.
If an I2C burst read operation reads past register address 0x12 the internal address
pointer “wraps” to address 0x03 and the contents of the SR Status Register are
returned.
10.4 WATCHDOG TIMER
When enabled (see MODE Register), the I2C watchdog timer prevents bus stall conditions in
cases where the master does not provide enough clocks to the slave to complete a read cycle.
During a read cycle, the slave that is actively driving the bus (SDA pin) will not release the bus
until 9 SCL clock edges are detected. While the SDA pin is held low by a slave open-drain
output, any other I2C devices attached to the sample bus will be unable to communicate. If the
slave does not see 9 SCL clocks from the master within the timeout period, the slave will
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