ZADCS0882_11 Datasheet, PDF (21/27 Pages) List of Unclassifed Manufacturers – 8-Bit, 300ksps, ADC Family

ZADCS0882/0842/0822
8-Bit, 300ksps, ADC Family
Field Programmable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC) may use this
operation mode.
Digital Timing
In general the clock frequency at SCLK may vary from 0.1MHz to 3.3MHz. Considering all telegram pauses or
other interruptions of a continuous clock at SCLK, each conversion must be completed within 1.2ms from the
falling clock edge of the eighth bit in the Control Byte. Otherwise the signal that was captured during
sample/hold may drop to noticeable affect the conversion result. Further detailed timing information on the
digital interface is provided in Table 8 and Figure 15.
Parameter
Symbol Conditions
Min
Typ
Max Unit
SCLK Periode
t _SCLK
303.0
ns
SCLK Pulse Width High
t _SCLKhigh
151.5
ns
SCLK Pulse Width Low
t _SCLKlow
151.5
ns
DIN to SCLK Setup
t _DinSetup
30
DIN to SCLK Hold
t _DinHold
10
nCS Fall to SCLK Setup
t _nCSSetup
30
SCLK Fall to
DOUT & SSTRB Hold
t _OutHold
C_Load = 20pF
10
SCLK Fall to
DOUT & SSTRB Valid
t _OutValid
C_Load = 20pF
nCS Rise to
DOUT & SSTRB Disable
t _OutDisable
C_Load = 20pF
10
nCS Fall to
DOUT & SSTRB Enable
t _OutEnable
C_Load = 20pF
nCS Pulse Width High
t _nCSHigh
100
Table 8: Timing Characterisitics (VDD = +2.7V to + 5.25V; _OP = _OPmin … _OPmax)
ns
ns
ns
ns
40
ns
60
ns
60
ns
ns
nCS
SCLK
DIN
SSTRB
DOUT
t _nCSSetup
t _SCLKhigh
t _SCL
t _DINsetup
t _OutEnable
t _OutEnable
t _SCLKlow
t _DINhold
t _nCSHig
t _OutValid
t _OutHold
Figure 15 Detailed Timing Diagram
Data Sheet
October 12, 2011
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
t _OutDisable
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