ZADCS0882_11 Datasheet, PDF (17/27 Pages) List of Unclassifed Manufacturers – 8-Bit, 300ksps, ADC Family

ZADCS0882/0842/0822
8-Bit, 300ksps, ADC Family
In bipolar mode, IN₊ can range from (IN_– - Vref/2) to
(IN_–+Vref/2) keeping the converter out of code
saturation. For instance, if IN_– is set to a constant DC
voltage of Vref/2, then IN₊ can vary from 0V to V_REF to
cover the entire code range. Lower or higher voltages of
CH0
IN₊ keep the output code at the minimum or maximum
code value.
CH1
CH2
Figure 7 shows the input voltage ranges in bipolar mode
when IN_– is set to a constant DC voltage.
CH3
CH4
CH5
As explained before, converters out of the ZADCS08x2
CH6
family can also be used to convert fully differential input
CH7
signals that change around a common mode input
voltage.
The bipolar mode is best used for such purposes since
it allows the input signals to be positive or negative in
relation to each other.
Shown configuration
A2 … A0 = 0x000
IN+
Converter
IN-
The common mode level of a differential input signal is
calculated V_CM = (V(IN₊)+ V(IN_–)) / 2. To avoid code
clipping or over steering of the converter, the common
mode level can change from ¼ V_REF … ¾ V_REF. Within
this range the peak to peak amplitude of the differential
input signal can be ± V_REF/2.
The average input current on the analog inputs depends
on the conversion rate. The signal source must be
capable of charging the internal sampling capacitors
(typically 16pF on each input of the converter: IN₊ and
IN_–) within the acquisition time t_ACQ to the required
accuracy. The equivalent input circuit in sampling mode
is shown in Figure 9.
COM
See Table 5 & Table 6
for Coding Schemes
SGL/DIF = HIGH
Figure 8: Block diagram of input multiplexer
The following equation provides a rough hand calculation for a source impedance R_S that is required to settle
out a DC input signal referenced to AGND with 8 bit accuracy in a given acquisition time
R_S

t _ACQ
6  C_IN
 R_SW
For example, if f_SCLK = 3.3MHz, the acquisition
time is t_ACQ = 758ns. Thus the output impedance
of the signal source R_S must be less than
CH0
CH1
C _HOLD+
R _SW
R_S

758ns
6  20pF
 3kΩ

3.32kΩ
CH2
CH3
CH4
If the output impedance of the source is higher
CH5
CH6
than the calculated maximum R_S the acquisition CH7
IN_{+ CIN}
4pF _16pF
AGND
C _HOLD-
3kΩ
R _SW
V _DC
time must be extended by reducing f_SCLK to ^COM
ensure 8 bit accuracy. Another option is to add a
capacitor of > 20nF to the individual input.
Channel
Multiplexer
IN_{- CIN}
4pF _16pF
3kΩ
Although this limits the bandwidth of the input
AGND
signal because an RC low pass filter is build
together with the source impedance, it may be
useful for certain applications.
Figure 9: Equivalent input circuit during sampling
Data Sheet
October 12, 2011
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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