ZADCS0882_11 Datasheet, PDF (12/27 Pages) List of Unclassifed Manufacturers – 8-Bit, 300ksps, ADC Family

ZADCS0882/0842/0822
8-Bit, 300ksps, ADC Family
1.5.2. Specific Parameters of ZADCS08x2V versions (with Internal Reference)
(VDD = +2.7V to + 5.25V; f_SCLK = 3.3MHz (50% duty cycle); 11 clocks/conversion cycle (300 ksps); _OP = _OPmin … _OPmax)
Parameter
Symbol Conditions
Min
Typ
Max Unit
Internal Reference at VREF
VREF Output Voltage
VREF Short-Circuit Current
VREF Temperature Coefficient
Load Regulation
Capacitive Bypass at VREF
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
T_A = + 25°C
0 to 0.2mA output load
2.480
4.7
0.047
External Reference at VREF (internal buffer disabled by V(REFADJ) = VDD)
VREF Input Voltage Range
1.0
VREF Input Current
VREF Input Resistance
Shutdown VREF Input Current
REFADJ Buffer Disable Threshold
VREF = 2.5V
11.5
VDD-
0.5
2.500
± 30
0.35
 1.5
180
14
2.520
30
± 50
V
mA
ppm/°C
mV
µF
µF
%
VDD +
50mV
V
215 µA
k
0.1 µA
V
External Reference at VREF_ADJ
Reference Buffer Gain
VREF_ADJ Input Current
Full Power Down
VREFADJ Input Current
Full Power-Down mode
2.00
±80 µA
0.1 µA
Power Requirements
Positive Supply Voltage
Positive Supply Current
ZADCS0882VI
ZADCS0842VI
ZADCS0822VI
Positive Supply Current
ZADCS0882VI
ZADCS0842VI
ZADCS0822VI
VDD
IDD
IDD
2.7
Operating Mode ext. VREF
VDD=3.6V ^{Operating Mode int. VREF}
Fast Power-Down
Full Power-Down
Operating Mode ext. VREF
VDD=5.2V ^{Operating Mode int. VREF}
Fast Power-Down
Full Power-Down
5.25 V
0.85 1.0 mA
1.3 1.4 mA
250
300
µA
0.5 4.0
1.00 1.3 mA
1.40 1.6 mA
250
300
µA
0.5 4.0
Data Sheet
October 12, 2011
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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