ISD9100 Datasheet, PDF (21/26 Pages) List of Unclassifed Manufacturers – ISD Cortex-M0 ChipCorder

ISD9100 Series Datasheet
R7
TIRSWR
Internal reset timeout after software-initiated
system reset
-
R8
TIRWDR Internal reset timeout after watchdog reset
-
*Notes:
2. It will be 6500us when use OSC_10K as the WDG clock.
6.3.4.1 Power-On Reset Timing
R1
VCCD
POR
(Internal)
Reset
(Internal)
R3
R2
R4
-
2
µs
-
3 *² µs
6.3.4.2 External Reset Timing (RESETN)
RESETN
Reset
(Internal)
R5
R6
6.3.4.3 Software Reset Timing
SW Reset
R7
Reset
(Internal)
6.3.4.4
Watchdog Reset Timing
WDOG Reset
(Internal)
R8
Reset
(Internal)
- 21 -
Release Date: January 8, 2016
Revision V1.41