ISD9100 Datasheet, PDF (11/26 Pages) List of Unclassifed Manufacturers – ISD Cortex-M0 ChipCorder

ISD9100 Series Datasheet
Pin No.
LQFP QFN ^{Pin Name}
48
33
I2S_SDI
PA.5
28
-
I2S_BCLK
PA.4
29
-
I2S_FS
PA.3
30
19 SPI_MISO0
I2C_SDA
PA.2
31
20
SPI_SSB0
32
21 VDD33
PA.1
33
22 SPI_SCLK
I2C_SCL
PA.0
34
23 SPI_MOSI0
MCLK
35
24 VCCLDO
PA.14
36
- SDCLK
SDCLKn
PA.13
PWM1
37
-
SPKM
I2S_BCLK
PA.12
PWM0
38
-
SPKP
I2S_FS
39
25 XO32K
40
26 XI32K
Pin Type
Alt
CFG
Description
I
1 Serial Data In for I2S interface
I/O
0 General purpose input/output pin; Port A, bit 5
I/O
1 Bit Clock for I2S interface
I/O
0 General purpose input/output pin; Port A, bit 4
I/O
1 Frame Sync Clock for I2S interface
I/O
0 General purpose input/output pin; Port A, bit 3
I
1 Master In, Slave Out channel 0 for SPI interface
I/O
2 Serial Data, I2C interface
I/O
0 General purpose input/output pin; Port A, bit 2
I/O
1 Slave Select Bar 0 for SPI interface
P
LDO Regulator Output. If used, a 1µF capacitor must be
placed to ground. If not used then tie to VCCD.
I/O
0 General purpose input/output pin; Port A, bit 1
I/O
1 Serial Clock for SPI interface
I/O
2 Serial Clock, I2C interface
I/O
0 General purpose input/output pin; Port A, bit 2
O
1 Master Out, Slave In channel 0 for SPI interface
O
2 Master clock output.
P
Power Supply for LDO, should be connected to VCCD
I/O
0 General purpose input/output pin; Port A, bit 14
O
1 Clock output for digital microphone mode.
O
2 Inverse Clock output for digital microphone mode.
I/O
0 General purpose input/output pin; Port A, bit 13
O
1 PWM1 Output.
O
2 Equivalent to SPK-.
I/O
3 Bit Clock for I2S interface
I/O
0 General purpose input/output pin; Port A, bit 12
O
1 PWM0 Output.
O
2 Equivalent to SPK+
I/O
3 Frame Sync Clock for I2S interface
O
32.768kHz Crystal Oscillator Output
I
32.768kHz Crystal Oscillator Input. Max Voltage 1.8V
- 11 -
Release Date: January 8, 2016
Revision V1.41