SI8450 Datasheet, PDF (20/36 Pages) List of Unclassifed Manufacturers – LOW POWER FIVE-CHANNEL DIGITAL ISOLATOR

Si8450/51/52/55
2.3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Table 12. Table 13 provides an
overview of the output states when the Enable pins are active.
Table 12. Si845x Logic Operation Table
V_I
Input^1,2
EN
Input^1,2,3,4
VDDI
State^1,5,6
VDDO
State^1,5,6
V_O Output^1,2
Comments
H
H or NC
P
P
H
Enabled, normal operation.
L
H or NC
P
P
L
X⁷
L
P
P
Hi-Z or L⁸ Disabled.
d _X7
H or NC
UP
de _X7
L
UP
P
L
Upon transition of VDDI from unpowered to pow-
ered, V_O returns to the same state as V_I in less
than 1 µs.
P
Hi-Z or L⁸ Disabled.
men _igns ^X7
X⁷
P
UP Undetermined Upon transition of VDDO from unpowered to pow-
ered, V_O returns to the same state as V_I within
1 µs, if EN is in either the H or NC state. Upon tran-
sition of VDDO from unpowered to powered, V_O
returns to Hi-Z within 1 µs if EN is L.
m s Notes:
1. VDDI and VDDO are the input and output power supplies. V_I and V_O are the respective input and output terminals. EN
o ^{e is the enable control input located on the same output side.}
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
c ^{D 3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si845x is}
operating in noisy environments.
e ^{4. No Connect (NC) replaces EN1 on Si8450. No Connects are not internally connected and can be left floating, tied to}
VDD, or tied to GND.
w _{5. “Powered” state (P) is defined as 2.70 V < VDD < 5.5 V.}
R _{e 6. “Unpowered” state (UP) is defined as VDD = 0 V.}
t ^{7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.}
8. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
o ^N (EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
N _for ^{"3. Errata and Design Migration Guidelines" on page 26 for more details.}
20
Rev. 1.5