SI8450 Datasheet, PDF (12/36 Pages) List of Unclassifed Manufacturers – LOW POWER FIVE-CHANNEL DIGITAL ISOLATOR

Si8450/51/52/55
Table 5. Electrical Characteristics¹
(V_DD1 = 2.70 V, V_DD2 = 2.70 V, T_A = –40 to 125 °C)
Parameter
Symbol Test Condition
Min
Typ
Max Unit
High Level Input Voltage
V_IH
2.0
—
—
V
Low Level Input Voltage
V_IL
—
—
0.8
V
High Level Output Voltage
V_OH
l_OH = –4 mA V_DD1,V_DD2 – 0.4 2.3
—
V
Low Level Output Voltage
V_OL
I_OL = 4 mA
—
0.2
0.4
V
Input Leakage Current
I_L
—
—
±10
µA
Output Impedance²
Z_O
—
85
—
Enable Input High Current
I_ENH
V_ENx = V_IH
—
2.0
—
d _{Enable Input Low Current}
I_ENL
V_ENx = V_IL
—
2.0
—
e _{DC Supply Current (All inputs 0 V or at supply)}
d ^{Si8450Ax, Bx, Si8455Bx}
V_DD1
n _{s VDD2}
e ^VDD1
n _VDD2
All inputs 0 DC
—
All inputs 0 DC
—
All inputs 1 DC
—
All inputs 1 DC
—
1.6
2.4
2.9
4.4
7.0
10.5
3.1
4.7
m _ig ^{Si8451Ax, Bx}
V_DD1
m ^{s VDD2}
V_DD1
o ^{e VDD2}
All inputs 0 DC
—
All inputs 0 DC
—
All inputs 1 DC
—
All inputs 1 DC
—
2.0
3.0
3.0
4.5
6.0
9.0
4.1
6.2
Si8452Ax, Bx
c ^D _VDD1
e ^VDD2
V_DD1
w _VDD2
All inputs 0 DC
—
All inputs 0 DC
—
All inputs 1 DC
—
All inputs 1 DC
—
2.3
3.5
2.7
4.1
5.4
8.1
4.7
7.1
R _{e 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)}
t _{Si8450Ax, Bx, Si8455Bx}
o ^{N V}DD1
V_DD2
N ^r Si8451Ax, Bx
fo ^VDD1
—
4.3
6.5
—
3.5
5.3
—
4.1
6.2

µA
µA
mA
mA
mA
mA
mA
V_DD2
—
4.0
6.0
Si8452Ax, Bx
V_DD1
V_DD2
—
4.1
6.2
mA
—
4.0
6.0
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to T_A = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. t_PSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 26 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.5