1010L-002 Datasheet, PDF (2/9 Pages) List of Unclassifed Manufacturers – DIGITAL ACCELEROMETER

Model 1010 Digital Accelerometer
SIGNAL DESCRIPTIONS
V_DD and GND (power): Pin 14 (V_DD) & pin 19 (GND). Additionally tie pins 3 & 11 to V_DD & pins 2, 5, 6 & 18 to GND.
CLK (input): Pin 8. Reference clock input. This hysteresis threshold input must be driven by a 50% duty cycle square wave
signal. Factory Calibration is performed at 250 kHz which is the recommended clock frequency for best results. Operation
at frequencies as low as 100 kHz or as high as 1 MHz are possible, however a slight bias shift may result.
CNT (output): Pin 10. Count output. A return-to-zero type digital
pulse stream whose pulse width is equal to the input CLK logic
high time. The CNT pulse rate increases with positive
acceleration. The device experiences positive (+1g)
acceleration with its lid facing up in the earth’s gravitational
field. _{_}T_{_}h_{_}is signal is meant to drive an up-counter directly.
DIR and DIR (output): Pins 12 & 16 respectively. Direction output. This output is updated at the fall of each clock cycle. It is
high during clock cycles when a high going CNT pulse is present and low during cycles when no CNT pulse is present. A
non-return-to-zero signal meant to control the count dir_e_c_tion (i.e. up or down) of a counter. DIR can be low pass filtered
to produce an analog measure of the acceleration. DIR is the complement of DIR and is provided for use in driving
differential transmission lines.
DV (input): Pin 4. Deflection Voltage. Normally left open. A test input that applies an electrostatic force to the sense element,
simulating a positive acceleration. The nominal voltage at this pin is aV_DD. DV voltages higher than required to bring the
output to positive full scale may cause device damage.
VR (input): Pin 3. Voltage Reference. Tie directly to V_DD (+5V). A 0.1µF bypass capacitor is recommended at this pin.
CLK/2 (output): Pin 15. Clock divided by 2. A buffered clock output whose frequency equals CLK divided by 2.
PERFORMANCE - by Model: V_DD=V_R=5.0 VDC, F_CLK=250kHz, T_C=25EC.
MODEL NUMBER
1010x-002 1010x-005 1010x-010 1010x-025 1010x-050 1010x-100 1010x-200
Input Range
±2
±5
±10
±25
±50
±100 ±200
Frequency Response (Nominal, 3 dB) 0 - 400 0 - 600 0 - 1000 0 - 1400 0 - 1600 0 - 1800 0 - 2000
Sensitivity (F_CLK=250kHz)
Max. Mechanical Shock (0.1 ms)
62.5
25.0
12.5
5.00
2.50
1.25 0.625
2000
5000
UNITS
g
Hz
kHz/g
g
PERFORMANCE - all Models: Unless otherwise specified V_DD=V_R=5.0 VDC, F_CLK=250kHz, T_C=25EC.
PARAMETER
MIN
TYP
MAX
UNITS
Cross Axis Sensitivity
2
3
%
Bias Calibration Error ¹
-002
-005 thru -200
2
1
4
2
% of F_CLK (span)
Bias Temperature Shift
-002
(T_C= -55 to +125EC) ¹
-005 thru -200
Scale Factor Calibration Error ^{1, 2}
Scale Factor Temperature Shift (T_C= -55 to +125EC) ¹
Non-Linearity
-002 thru -100
(-90 to +90% of Full Scale) ^{1, 2}
-200
150
400
100
300
1
2
+300
0.5
1.0
0.7
1.5
(ppm of F_CLK)/EC
%
ppm/EC
% of span
Power Supply Rejection Ratio (V_DD=V_R)
Operating Voltage (V_DD vs GND)
Operating Current (I_DD+I_VR) ¹
Clock Input Voltage Range (with respect to GND)
Mass: ‘L’ package (add 0.06 grams for ‘J’ package)
40
4.5
5.0
5.5
2
3
-0.5
V_DD+0.5
0.62
dB
Volts
mA
Volts
grams
Note 1: Tighter tolerances available on special order.
Note 2: 100g and greater versions are tested from -65 to +65g.
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
Silicon Designs, Inc. ! 1445 NW Mall Street, Issaquah, WA 98027-5344 ! Phone: [phone] ! Fax: [phone]
web site: www.silicondesigns.com
[page 2]
Mar 07