LM3S3748 Datasheet, PDF (164/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Internal Memory
Register to be Committed FMA Value Data Source
USER_DBG
0x7510.0000 FMD
a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris^® device.
8.4 Register Map
Table 8-3 on page 164 lists the ROM Controller registers and the Flash memory and control registers.
The offset listed is a hexadecimal increment to the register's address. The ROM Controller registers
are relative to the System Control base address of 0x400F.E000. The FMA, FMD, FMC, FCRIS,
FCIM, and FCMISC registers are relative to the Flash control base address of 0x400F.D000. The
FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the System
Control base address of 0x400F.E000.
Table 8-3. Flash Register Map
Offset Name
Type
Reset
Description
ROM Registers (System Control Offset)
0x0F0 RMCTL
R/W1C
Flash Registers (Flash Control Offset)
0x000 FMA
R/W
0x004 FMD
R/W
0x008 FMC
R/W
0x00C FCRIS
RO
0x010 FCIM
R/W
0x014 FCMISC
R/W1C
Flash Registers (System Control Offset)
0x0F4 RMVER
RO
0x130 FMPRE0
R/W
0x200 FMPRE0
R/W
0x134 FMPPE0
R/W
0x400 FMPPE0
R/W
0x140 USECRL
R/W
0x1D0 USER_DBG
R/W
0x1E0 USER_REG0
R/W
0x1E4 USER_REG1
R/W
0x1E8 USER_REG2
R/W
0x1EC USER_REG3
R/W
0x204 FMPRE1
R/W
0x208 FMPRE2
R/W
-
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0xFFFF.FFFF
0xFFFF.FFFF
0xFFFF.FFFF
0xFFFF.FFFF
0x31
0xFFFF.FFFE
0xFFFF.FFFF
0xFFFF.FFFF
0xFFFF.FFFF
0xFFFF.FFFF
0xFFFF.FFFF
0x0000.0000
ROM Control
Flash Memory Address
Flash Memory Data
Flash Memory Control
Flash Controller Raw Interrupt Status
Flash Controller Interrupt Mask
Flash Controller Masked Interrupt Status and Clear
ROM Version Register
Flash Memory Protection Read Enable 0
Flash Memory Protection Read Enable 0
Flash Memory Protection Program Enable 0
Flash Memory Protection Program Enable 0
USec Reload
User Debug
User Register 0
User Register 1
User Register 2
User Register 3
Flash Memory Protection Read Enable 1
Flash Memory Protection Read Enable 2
See
page
166
167
168
169
171
172
173
175
176
176
177
177
174
178
179
180
181
182
183
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164
April 08, 2008
Preliminary