LM3S3748 Datasheet, PDF (122/753 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Bit/Field
17
16
15
14
13
12
11:9
8
7:6
5
4
3:2
1
Name
TIMER1
TIMER0
reserved
I2C1
reserved
I2C0
reserved
QEI0
reserved
SSI1
SSI0
reserved
UART1
Type
R/W
R/W
RO
R/W
RO
R/W
RO
R/W
RO
R/W
R/W
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Timer 1 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 1. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
Timer 0 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 0. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C1 Clock Gating Control. This bit controls the clock gating for I2C
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C0 Clock Gating Control. This bit controls the clock gating for I2C
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
QEI0 Clock Gating Control. This bit controls the clock gating for QEI
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI1 Clock Gating Control. This bit controls the clock gating for SSI
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
SSI0 Clock Gating Control. This bit controls the clock gating for SSI
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART1 Clock Gating Control. This bit controls the clock gating for UART
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
122
April 08, 2008
Preliminary