N79E855 Datasheet, PDF (155/180 Pages) List of Unclassifed Manufacturers – Microcontroller

N79E855/854 Data Sheet
24.3 RST Pin Reset
The hardware reset input is RST pin which is the input with a Schmitt trigger. A hardware reset is accomplished by
holding the RST pin low for at least two machine-cycles to ensure detection of a valid hardware reset signal. The reset
circuitry then synchronously applies the internal reset signal. Thus the reset is a synchronous operation and requires the
clock to be running to cause an external reset.
Once the device is in reset condition, it will remain so as long as RST pin is 1. After the RST low is removed, the CPU
will exit the reset state with in two machine-cycles and begin code executing from address 0000H. There is no flag
associated with the RST pin reset condition. However since the other reset sources have flags, the external reset can be
considered as the default reset if those reset flags are cleared.
If a RST pin reset applies while CPU is in Power-down mode, the way to trigger a hardware reset is slightly different.
Since the Power-down mode stops clock system, the reset signal will asynchronously cause the clock system resuming.
After the clock system is stable, CPU will enter into the reset state, then exit and start to execute program code from
address 0000H.
Note: Because reset pin has internal pull-up resistor (about 200KΩ at V_DD = 5V), this pin cannot be floating. Reset
pin should be connected to a 100Ω pull-up resistor and a 10uF pull-low capacitor.
24.4 Watchdog Timer Reset
The Watchdog Timer is a free running timer with programmable time-out intervals. The user can clear the Watchdog
Timer at any time, causing it to restart the count. When the selected time-out occurs, the Watchdog Timer will reset the
system directly. The reset condition is maintained via hardware for two machine-cycles. After the reset is removed the
device will begin execution from 0000H.
Once a reset due to Watchdog Timer occurs the Watchdog Timer reset flag WDTRF (WDCON0.3) will be set. This bit
keeps unchanged after any reset other than a power-on reset. The user may clear WDTRF via software.
April 23, 2014
Page 155 of 180
Revision A2.5