PL3120 Datasheet, PDF (1/13 Pages) List of Unclassifed Manufacturers – Line Smart Transceivers

PL 3120^® and PL 3150^® Power
®
Line Smart Transceivers
Feature
• Combines an ANSI-709.2 compliant Power Line Transceiver with an ANSI 709.1
compliant Neuron® 3120 or Neuron 3150 processor core
• Designed to comply with FCC, Industry Canada, Japan MPT, and European
CENELEC EN 50065-1 power line communications regulations
• Supports CENELEC A-band and C-band operation
• Dual carrier frequency mode and digital signal processing
• 4K Bytes of embedded EEPROM for application code and configuration data on
the PL 3120 Power Line Smart Transceiver and 0.5K Bytes of embedded EEP-
ROM for configuration data on the PL 3150 Power Line Smart Transceiver
• Interface for external memory for applications with larger memory requirements
(PL 3150 Power Line Smart Transceiver only)
• 2K Bytes of embedded RAM for buffering network data and network variables
• Full duplex hardware UART and SPI serial interfaces
• 12 I/O pins with 38 programmable standard I/O modes to minimize external
interface circuitry
• -40 to +85°C operating temperature range
Overview
The PL 3120 and PL 3150 Power Line Smart Transceivers integrate a Neuron processor core
with a power line transceiver, making them ideal for appliance, audio/video, lighting, heat-
ing/cooling, security, metering, and irrigation applications. Essentially a system-on-a-chip, the
Power Line Smart Transceivers feature a highly reliable narrow-band power line transceiver,
an 8-bit Neuron processor core for running applications and managing network communica-
tions, a choice of on-board or external memory, and an extremely small form factor – all at a
price that is compelling for even the most cost-sensitive consumer product applications.
A Global Product
Compliant with FCC, Industry Canada, Japan MPT, and European CENELEC EN50065-1
regulations, the PL 3120 and PL 3150 Power Line Smart Transceivers can be used in applica-
tions worldwide.
The Power Line Smart Transceivers implement the CENELEC access protocol, which can be
enabled or disabled by the user. This eliminates the need for users to develop the complex
timing and access algorithms mandated under CENELEC EN50065-1. Additionally, the Power
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