IT8705AF Datasheet, PDF (94/185 Pages) List of Unclassifed Manufacturers – Simple Low Pin Count Input/Output (simple LPC I/O)

IT8705F
9.5.3.2 Register Description
9.5.3.2.1Configuration Register (Index=00h, Default=18h)
Bit
R/W
Description
7
R/W Initialization. A “1” restores all registers to their individual default values, except the
Serial Bus Address register. This bit clears itself when the default value is “0.”
6
R/W Update VBAT Voltage Reading
5
R/W COPEN# cleared; Write “1” to clear COPEN#
4
R Read Only, Always “1.”
3
R/W INT_Clear. A “1” disables the SMI# and IRQ outputs with the contents of interrupt status
bits remain unchanged.
2
R/W IRQ enables the IRQ Interrupt output
1
R/W SMI# Enable. A “1” enables the SMI# Interrupt output.
0
R/W Start. A “1” enables the startup of monitoring operations while a “0” sends the monitoring
operation in the STANDBY mode.
9.5.3.2.2 Interrupt Status Register 1 (Index=01h, Default=00h)
Reading this register will clear itself following a read access.
Bit
R/W
Description
7-5
R
Reserved
4
R A “1” indicates a Case Open event has occurred.
3
R
Reserved
2-0
R A “1” indicates the FAN_TAC3-1 Count limit has been reached.
9.5.3.2.3 Interrupt Status Register 2 (Index=02h, Default=00h)
Reading this register will clear itself after the read operation is completed.
Bit
R/W
Description
7-0
R
A “1” indicates a High or Low limit of VIN7-0 has been reached.
9.5.3.2.4 Interrupt Status Register 3 (Index=03h, Default=00h)
Reading this register will clear itself following a read access.
Bit
R/W
Description
7-3
R
Reserved
2-0
R A “1” indicates a High or Low limit of Temperature 3-1 has been reached.
9.5.3.2.5 SMI# Mask Register 1 (Index=04h, Default=00h)
Bit
R/W
Description
7-6
R/W Reserved
4
R/W A “1” disables the Case Open Intrusion interrupt status bit for SMI#.
3
R/W Reserved
2-0
R/W A “1” disables the FAN_TAC3-1 interrupt status bit for SMI#.
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IT8705F V0.4