IT8705AF Datasheet, PDF (72/185 Pages) List of Unclassifed Manufacturers – Simple Low Pin Count Input/Output (simple LPC I/O)

IT8705F
8.9.19 SMI# Control Register (Index=F0h, Default=00h)
Bit
Description
7 Reserved
6 SMI# of MIDI IRQ Enable
Enable the generation of an SMI# due to MIDI Port’s IRQ (EN_CIRQ).
5 SMI# of CIR IRQ Enable
Enable the generation of an SMI# due to CIR’s IRQ (EN_CIRQ).
4 SMI# of EC IRQ Enable
Enable the generation of an SMI# due to Environment Controller’s IRQ (EN_ECIRQ).
3 SMI# of PPORT IRQ Enable
Enable the generation of an SMI# due to Parallel Port’s IRQ (EN_PIRQ).
2 SMI# of UART2 IRQ Enable
Enable the generation of an SMI# due to Serial Port 2’s IRQ (EN_S2IRQ).
1 SMI# of UART1 IRQ Enable
Enable the generation of an SMI# due to Serial Port 1’s IRQ (EN_S1IRQ).
0 SMI# of FDC IRQ Enable
Enable the generation of an SMI# due to FDC’s IRQ (EN_FIRQ).
8.9.20 SMI# Status Register (Index=F2h, Default=00h)
This register is used to read the status of SMI# inputs.
Bit
Description
7 Reserved
6 The generation of an SMI# due to MIDI Port’s IRQ.
5 The generation of an SMI# due to CIR’s IRQ.
4 The generation of an SMI# due to Environment Controller’s IRQ.
3 The generation of an SMI# due to Parallel Port’s IRQ.
2 The generation of an SMI# due to Serial Port 2’s IRQ.
1 The generation of an SMI# due to Serial Port 1’s IRQ.
0 The generation of an SMI# due to FDC’s IRQ.
8.9.21 SMI# Pin Mapping Register (Index=F5h, Default=00h)
Bit
Description
7 Reserved
6 SMI# Direct Access Enable
0: Disable SMI# Direct Access (default)
1: Enable SMI# Direct Access.
5-0 SMI# Pin Location
Please see Location mapping table ^note3.
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IT8705F V0.4