IT8705AF Datasheet, PDF (133/185 Pages) List of Unclassifed Manufacturers – Simple Low Pin Count Input/Output (simple LPC I/O)

Functional Description
9.6.14 Low Power Mode
When writing a 1 to the bit 6 of the DSR, the controller is set to low power mode immediately. All the clock
sources including Data Separator, Microcontroller, and Write precompensation unit will be gated. The FDC
can be resumed from the low-power state in two ways. One is a software reset via the DOR or DSR; and the
other is a read or write to either the Data Register or Main Status Register. The second method is more
preferred since all internal register values are retained.
9.7 Serial Port (UART) Register Description
The IT8705F incorporates two enhanced serial ports that perform serial to parallel conversion on received
data, and parallel to serial conversion on transmitted data. Each of the serial channels individually contains a
programmable baud rate generator, which is capable of dividing the input clock by a number ranging from 1 to
65535. The data rate of each serial port can also be programmed from 115.2K baud down to 50 baud. The
character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd, stick or no parity; and
privileged interrupts.
Register
Data
Control
Status
Table 9-25. Serial Channel Registers
DLAB* Address
READ
WRITE
0 Base + 0h RBR (Receiver Buffer Register) TBR (Transmitter Buffer Register)
0 Base + 1h IER (Interrupt Enable Register) IER
x Base + 2h IIR (Interrupt Identification
FCR (FIFO Control Register)
x Base + 3h ^Register)
LCR
x Base + 4h ^{LCR (Line Control Register)}
MCR
1 Base + 0h ^{MCR (Modem Control Register)} DLL
1 Base + 1h ^{DLL (Divisor Latch LSB)}
DLM
DLM (Divisor Latch MSB)
x Base + 5h LSR (Line Status Register)
LSR
x Base + 6h MSR (Modem Status Register)
MSR
x Base + 7h SCR (Scratch Pad Register)
SCR
* DLAB is bit 7 of the Line Control Register.
9.7.1 Data Registers
The TBR and RBR individually holds from five to eight data bits. If the transmitted data is less than eight bits,
it aligns to the LSB. Either received or transmitted data is buffered by a shift register, and is latched first by a
holding register. The bit 0 of any word is first received and transmitted.
(1) Receiver Buffer Register (RBR) (Read only, Address offset=0, DLAB=0)
This register receives and holds the incoming data. It contains a non-accessible shift register which converts
the incoming serial data stream into a parallel 8-bit word.
(2) Transmitter Buffer Register (TBR) (Write only, Address offset=0, DLAB=0)
This register holds and transmits the data via a non-accessible shift register, and converts the outgoing
parallel data into a serial stream before transmission.
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IT8705F V0.4