IT8705AF Datasheet, PDF (147/185 Pages) List of Unclassifed Manufacturers – Simple Low Pin Count Input/Output (simple LPC I/O)

Functional Description
(3) EPP DATA WRITE
1. The host writes a byte to the EPP Data Port (Base address +04H - 07H). The chip drives D0- D7 onto
PD0 -PD7.
2. The chip asserts WRITE# (STB#) and DSTB# (AFD#) after IOW becomes active.
3. The peripheral de-asserts WAIT#, indicating that the chip may begin the termination of this cycle. Then,
the chip de-asserts DSTB#, latches the data from D0 - D7 to the PD bus, allowing the host to complete
the I/O write cycle.
4. The peripheral asserts WAIT#, indicating that it acknowledges the termination of the cycle. Then, the
chip de-asserts writes to terminate the cycle.
(4) EPP DATA READ
1. The host reads a byte from the EPP DATA Port. The chip drives PD bus to tri-state for the peripheral
to drive.
2. The chip asserts DSTB# after IOR becomes active.
3. The peripheral drives PD bus valid and de-asserts WAIT#, indicating that the chip may begin the
termination of this cycle. Then, the chip de-asserts DSTB#, latches the data from PD bus to D0 - D7,
allowing the host to complete the I/O read cycle.
4. The peripheral tri-states the PD bus and then asserts WAIT#, indicating that it acknowledges the
termination of the cycle.
9.8.3 ECP Mode Operation
This mode is both software and hardware compatible with the existing parallel ports, allowing ECP to be used
as a standard LPT port when the ECP mode is not required. It provides an automatic high-burst-bandwidth
channel that supports DMA or the ECP mode in both forward and reverse directions. A 16-byte FIFO is
implemented in both forward and reverse directions to smooth data flow and increase the maximum
bandwidth allowed. The port supports automatic handshaking for the standard parallel port to improve
compatibility and expedite the mode transfer. It also supports run-length encoded (RLE) decompression in
hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that
indicates how many times a byte has been repeated. The IT8705F does not support hardware RLE
compression. For a detailed description, please refer to "Extended Capabilities Port Protocol and ISA
Interface Standard".
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IT8705F V0.4