IT8702F Datasheet, PDF (94/173 Pages) List of Unclassifed Manufacturers – Super-Low Pin Count Input/Output (LPC I/O)

IT8702F
7
R Reserved.
Should write ”0”.
6-0
R/W 128 steps of PWM control.
9.5.2.2.32 FAN_CTL5 PWM Control Register (Index=89h, Default=00h)
Bit
R/W
7
R Reserved.
Should write ”0”.
6-0
R/W 128 steps of PWM control.
Description
9.5.3 Operation
9.5.3.1 Power On RESET and Software RESET
When the system power is first applied, the FAN Controller performs a “power on reset” on the registers
which are returned to default values (due to system hardware reset). Except the function of the Serial Bus
Interface Address register, a software reset (bit 7 of Configuration register) is able to accomplish all the
functions as the hardware reset does.
9.5.3.2 Fan Tachometer
The Fan Tachometer inputs gate a 22.5 kHz clock into an 8-bit or a16-bit counter (maximum count=255 or
65535) for one period of the input signals. Several divisors, located in FAN Divisor Register, are provided for
FAN_TAC1, FAN_TAC2, and FAN_TAC3, and are used to modify the monitoring range. Counts are based on
2 pulses per revolution tachometer output.
RPM = 1.35 X 10⁶ / (Count X Divisor)
The maximum input signal range is from 0 to VCC. The additional application is needed to clamp the input
voltage and current.
9.5.3.3 Interrupt of the FAN Controller
The FAN Controller generates interrupts as a result of each of its Limit registers on FAN monitor. All the
interrupts are indicated in two Interrupt Status Registers. The IRQ and SMI# outputs have individual mask
registers. These two Interrupts can also be enabled/disabled in the Configuration Register. The Interrupt
Status Registers will be reset after being read. When the Interrupt Status Registers are cleared, the Interrupt
lines will also be cleared. When a read operation is completed before the completion of the monitoring loop
sequence, it indicates an Interrupt Status Register has been cleared. Due to slow monitoring sequence, the
FAN Controller needs 1.5 seconds to allow all the FAN Controller Registers to be safely updated between
completed read operations. When the bit 3 of the Configuration Register is set to high, the Interrupt lines are
cleared and the monitoring loop will be stopped. The loop will resume when this bit is cleared.
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IT8702F V0.5