IT8702F Datasheet, PDF (120/173 Pages) List of Unclassifed Manufacturers – Super-Low Pin Count Input/Output (LPC I/O)

IT8702F
9.6.12.13 INVALID
The INVALID command indicates when an undefined command has been sent to FDC. The FDC will set the
bit 6 and the bit 7 in the Main Status Register to 1 and terminate the command without issuing an interrupt.
9.6.13 DMA Transfers
DMA transfers are enabled by the SPECIFY command and are initiated by the FDC by activating the LDRQ#
cycle during a DATA TRANSFER command. The FIFO is enabled directly by asserting the LPC DMA cycles.
9.6.14 Low Power Mode
When writing a 1 to the bit 6 of the DSR, the controller is set to low power mode immediately. All the clock
sources including Data Separator, Microcontroller, and Write precompensation unit, will be gated. The FDC
can be resumed from the low-power state in two ways: one is a software reset via the DOR or DSR, and the
other is a read or write to either the Data Register or Main Status Register. The second method is more
preferred since all internal register values are retained.
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IT8702F V0.5