IT8702F Datasheet, PDF (124/173 Pages) List of Unclassifed Manufacturers – Super-Low Pin Count Input/Output (LPC I/O)

IT8702F
(3) FIFO Control Register (FCR) (Write Only, Address offset=2)
This register is used to enable, clear the FIFO, and set the RCVR FIFO trigger level.
Table 9-28. FIFO Control Register Description
Bit Default
Description
7-6
-
Receiver Trigger Level Select
These bits set the trigger levels for the RCVR FIFO interrupt.
5-4
0
Reserved
3
0
This bit does not affect the Serial Channel operation. RXRDY and TXRDY functions
are not available on this chip.
2
0
Transmitter FIFO Reset
This self-clearing bit clears all contents of the XMIT FIFO and resets its related
counter to 0 via a logic "1."
1
0
Receiver FIFO Reset
Setting this self-clearing bit to a logic 1 clears all contents of the RCVR FIFO and
resets its related counter to 0 (except the shift register).
0
0
FIFO Enable
XMIT and RCVR FIFOs are enabled when this bit is set high. XMIT and RCVR FIFOs
are disabled and cleared respectively when this bit is cleared to low. This bit must be a
logic 1 if the other bits of the FCR are written to, or they will not be properly
programmed. When this register is switched to non-FIFO mode, all its contents are
cleared.
Table 9-29. Receiver FIFO Trigger Level Encoding
FCR (7) FCR (6)
RCVR FIFO Trigger Level
0
0
1 byte
0
1
4 bytes
1
0
8 bytes
1
1
14 bytes
(4) Divisor Latches (DLL, DLM) (Read/Write, Address offset=0,1 DLAB=0)
Two 8-bit Divisor Latches (DLL and DLM) store the divisor values in a 16-bit binary format. They are loaded
during the initialization to generate a desired baud rate.
(5) Baud Rate Generator (BRG)
Each serial channel contains a programmable BRG which can take any clock input (from DC to 8 MHz) to
generate standard ANSI/CCITT bit rates for the channel clocking with an external clock oscillator. The DLL or
16
DLM is a number of 16-bit format, providing the divisor range from 1 to 2 to obtain the desired baud rate.
The output frequency is 16X data rate.
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IT8702F V0.5