MC80F0204 Datasheet, PDF(86/126 Page) List of Unclassifed Manufacturers

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MC80F0204 Datasheet, PDF (86/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

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MC80F0104/0204

Preliminary

R/W R/W R/W R/W R/W R/W R/W R/W

IRQH INT0IF INT1IF INT2IF INT3IF UARTRIF UARTTIF SIOIF T0IF

MSB

LSB

ADDRESS: 0ECH

INITIAL VALUE: 0000 0000B

Timer/Counter 0 interrupt request flag

Serial Communication interrupt request flag

UART Txx interrupt request flag

UART Rx interrupt request flag

External interrupt 3 request flag

External interrupt 2 request flag

External interrupt 1 request flag

External interrupt 0 request flag

IRQL

R/W R/W R/W

T1IF T2IF T3IF

- R/W R/W - R/W

- ADCIF WDTIF - BITIF

ADDRESS: 0EDH

INITIAL VALUE: 000- 00-0B

MSB

LSB

Basic Interval Timer interrupt request flag

Watchdog timer interrupt request flag

A/D Converter interrupt request flag

Timer/Counter 3 interrupt request flag

Timer/Counter 2 interrupt request flag

Timer/Counter 1 interrupt request flag

Figure 18-3 Interrupt Request Flag Register

18.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted

or the interrupt latch is cleared to â0â by a reset or an in-

struction. Interrupt acceptance sequence requires 8 cycles

of fXIN (2Âµs at fXIN=4MHz) after the completion of the

18.1.1 Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to

â0â to temporarily disable the acceptance of any follow-

ing maskable interrupts. When a non-maskable inter-

rupt is accepted, the acceptance of any following

interrupts is temporarily disabled.

2. Interrupt request flag for the interrupt source accepted is

cleared to â0â.

3. The contents of the program counter (return address)

current instruction execution. The interrupt service task is

terminated upon execution of an interrupt return instruc-

tion [RETI].

and the program status word are saved (pushed) onto the

stack area. The stack pointer decreases 3 times.

4. The entry address of the interrupt service program is

read from the vector table address and the entry address

is loaded to the program counter.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

Mar. 2005 Ver 0.2

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