MC80F0204 Datasheet, PDF (58/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0104/0204
Preliminary
The Timer/Counter register is increased in response inter-
nal or external input. This counting function is same with
normal timer mode, and Timer interrupt is generated when
timer register T0 (T1, T2, T3) increases and matches
TDR0 (TDR1, TDR2, TDR3).
This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.
For example, in Figure 13-14 , the pulse width of captured
signal is wider than the timer data value (FF_H) over 2
times. When external interrupt is occurred, the captured
value (13_H) is more little than wanted value. It can be ob-
tained correct value by counting the number of timer over-
flow occurrence.
Timer/Counter still does the above, but with the added fea-
ture that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1,T2,T3), to
be captured into registers CDRx (CDR0, CDR1, CDR2,
CDR3), respectively. After captured, Timer x register is
cleared and restarts by hardware. It has three transition
modes: "falling edge", "rising edge", "both edge" which
are selected by interrupt edge selection register IEDS. Re-
fer to “18.4 External Interrupt” on page 86. In addition, the
transition at INTn pin generate an interrupt.
Note: The CDRn and TDRn are in same address.In the capture
mode, reading operation is read the CDRn, not TDRn because
path is opened to the CDRn.
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Mar. 2005 Ver 0.2