MC80F0224 Datasheet, PDF(82/128 Page) List of Unclassifed Manufacturers

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MC80F0224 Datasheet, PDF (82/128 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

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MC80F0208/16/24

Preliminary

17.2 Serial Interface Configuration

The UART interface consists of the following hardware.

Item

Configuration

Transmit shift register (TXR)

Receive buffer register (RXR)

Receive shift register

Control

Serial interface mode register (ASIMR)

Serial interface status register (ASISR)

Baudrate generator control register (BRGCR)

Table 17-1 Serial Interface Configuration

Transmit shift register (TXR)

This is the register for setting transmit data. Data written to TXR0

is transmitted as serial data. When the data length is set as 7 bit,

bit 0 to 6 of the data written to TX0 are transferred as transmit da-

ta. Writing data to TXR0 starts the transmit operation.

TXR0 can be written by an 8 bit memory manipulation instruc-

tion. It cannot be read. The RESET input sets TXR0 to 0FFH.

Note: Do not write to TXR during a transmit operation. The

same address is assigned to TXR and the receive buffer

Receive buffer register (RXR)

This register is used to hold receive data. When one byte of data

is received, one byte of new receive data is transferred from the

receive shift register (RXSR). When the data length is set as 7

bits, receive data is sent to bits 0 to 6 of RXR0. In this case, the

MSB of RXR always becomes 0.

RXR can be read by an 8 bit memory manipulation instruction. It

cannot be written. The RESET input sets RXR0 to 00H.

Note: The same address is assigned to RXR and the

transmit shift register (TXR). During a write operation, val-

ues are written to TXR.

Receive shift register

This register converts serial data input via the RxD pin to paral-

leled data. When one byte of data is received at this register can-

not be manipulated directly by a program.

Asynchronous serial interface mode register

(ASIMR)

This is an 8 bit register that controls UART serial transfer opera-

tion. ASIMR is set by a 1 bit or 8 bit memory manipulation in-

truction. The RESET input sets ASIMR to 0000_-00-B. Table 17-

4 shows the format of ASIMR.

Note: Do not switch the operation mode until the current

serial transmit/receive operation has stopped.

ASIMR0

R/W R/W R/W R/W R/W R/W R/W

TXE0 RXE0 PS01 PS00 BTC- L SL0 ISRM0 -

ADDRESS: 0E6H

INITIAL VALUE: 0000 -00-B

UART0 Receive interrupt request is issued when an error occurs bit

0: Receive Completion Interrupt Control When Error occurs

1: Receive completion interrupt request is not issued when an error occur

UART0 Stop Bit Length for Specification for Transmit Data bit

0: 1 bit

1: 2 bit

UART0 Parity Bit Specification bit

00: No parity

01: Zero parity always added during transmission.

No parity detection during reception (parity errors do not occur)

10: Odd parity

11: Even parity

UART0 Tx/Rx Enable bit

00: Not used UART0 (R46, R47)

01: UART0 Receive only Mode(RxD, R47)

10: UART0 Transmit only Mode(R46, TxD)

11: UART0 Receive & Transmit Mode(RxD, TxD)

Figure 17-4 Asynchronous Serial Interface Mode register (ASIMR0) Format

MAR. 2005 Ver 0.2

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