MC80F0224 Datasheet, PDF (36/128 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0208/16/24
Preliminary
Address Name
Bit 7
Bit 6
Bit 5
0FFH
Reserved
EE6H² ASIMR1
TXE1
RXE1
PS11
EE7H² ASISR1
-
-
-
EE8H² BRGCR1
-
TPS12 TPS11
RXR1
EE9H²
TXR1
UART1 Receive Buffer Register
UART1 Transmit Shift Register
Bit 4
PS10
-
TPS10
Bit 3
Bit 2
Bit 1
Bit 0
-
-
MLD13
SL1
PE1
MLD12
ISRM1
FE1
MLD11
-
OVE1
MLD10
Table 8-2 Control Register Function Description
1. The register BITR and CKCTLR are located at same address. Address F2H is read as BITR, written to CKCTLR.
Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be
accessed by register operation instruction such as "LDM dp,#imm".
2. The UART1 control register ASIMR1,ASISR1, BRGCR1,RXR1 and TXR1 are located at EE6H ~ EE9H address.
These address must be accessed(read and written) by absolute addressing manipulation instruction.
8.4 Addressing Mode
The MC800 series MCU uses six addressing modes;
• Register addressing
• Immediate addressing
• Direct page addressing
• Absolute addressing
• Indexed addressing
• Register-indirect addressing
8.4.1 Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
8.4.2 Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data imme-
diately.
Example:
0435 ADC #35H
MEMORY
04
A+35H+C → A
35
When G-flag is 1, then RAM address is defined by 16-bit address
which is composed of 8-bit RAM paging register (RPR) and 8-bit
immediate data.
Example: G=1
E45535 LDM 35H,#55H
0135H
data
➊ ^~~
0F100H
E4
0F101H
55
0F102H
35
data ← 55H
~~
➋
8.4.3 Direct Page Addressing → dp
In this mode, a address is specified within direct page.
Example; G=0
32
MAR. 2005 Ver 0.2