MA828 Datasheet, PDF (8/16 Pages) List of Unclassifed Manufacturers – THREE-PHASE PULSE WIDTH MODULATION WAVEFORM GENERATOR

MA828
AMP₇ AMP₆ AMP₅ AMP₄ AMP₃ AMP₂ AMP₁ AMP₀
AMPLITUDE
SELECT WORD
AMP₇ = MSB
AMP0 = LSB
Fig.14 Temporary register R2
Amplitude selection
The power wavefortm amplitude is determined by scaling the
amplitude of the waveform samples stored in the ROM by the
value of the 8-bit amplitude select word (AMP).
The percentage amplitude control is given by:
A
where
A
Power Amplitude, A_POWER
= decimal value of AMP.
=
225
3
100%
POWER-UP C0NDITIONS
All bits in both the Initialisation and Control registers power-
up in the low state. This means that Counter Reset (CR) is active
and a 50% duty cycle will be output from all PWM outputs until
further initialising action is taken. Holding RST low or using the
SET TRIP input will ensure that the PWM outputs remain inactive
(i.e., low) during this period.
MA828 PROGRAMMING EXAMPLE
The following example assumes that a master clock of 12·288
MHz is used (12·288 MHz crystals are readily available). This
clock frequency will allow a maximum carrier frequency of
24 kHz and a maximum power frequency of 4 kHz.
Initialisation Register Programming Example
A power waveform range of up to 250Hz is required with a
carrier frequency of 6kHz, a pulse deletion time of 10µs and an
underlap of 5µs.
1. Setting the carrier frequency
The carrier frequency should be set first as the power
frequency, pulse deletion time and pulse delay time are all
defined relative to the carrier frequency.
We must calculate the value of n that will give the required
carrier frequency:
f_CARR
=
k
5123n
⇒n=
k
= ^{12·2883106} = 4
5123f_CARR 51236310³
From Table 4, n = 4 corresponds to a 3-bit CFS word of
010 in temporary register R1.
2. Setting the power frequency range
We must calculate the value of m that will give the required
power frequency:
f_RANGE
=
f_CARR
384
3
m
⇒ m = ^fRANGE3384 = ^2503384 = 16
f_CARR
6310³
From Table 5, m = 16 corresponds to a 3-bit FRS word of 100
in temporary register R1.
3. Setting the pulse delay time
As the pulse delay time affects the actual minimum pulse
width seen at the PWM outputs, it is sensible to set the pulse
delay time before the pulse deletion time, so that the effect of the
pulse delay time can be allowed for when setting the pulse
deletion time.
8
We must calculate the value of pdy that will give the required
pulse delay time:
pdy
t_pdy = _fCARR3512
⇒ pdy = t_pdy3f_CARR3512
= 5310²⁶36310³3512 = 15·4
However, the value of pdy must be an integer. As the purpose
of the pulse delay is to prevent ‘shoot-through’ (where both top
and bottom arms of the inverter are on simultaneously), it is
sensible to round the pulse delay time up to a higher, rather than
a lower figure.
Thus, if we assign the value 16 to pdy this gives a delay time
of 5·2µs. From Table 6, pdy = 16 corresponds to a 6-bit PDY
word of 110000 in temporary register R2.
4. Setting the pulse deletion time
In setting the pulse deletion time (i.e., the minimum pulse
width) account must be taken of the pulse delay time, as the
actual minimum pulse width seen at the PWM outputs is equal
to t_pd2t_pdy.
Therefore, the value of the pulse deletion time must, in this
instance, be set 5·2µs longer than the minimum pulse length
required
Minimum pulse length required = 10µs
∴ tPD to be set to 10µs15·2µs = 15·2µs
Now,
pdt
t_pd = _fCARR3512
⇒ pdt = f_pd3f_CARR3512
= 15·2310²⁶36310³3512 = 46·7
Again, pdt must be an integer and so must be either rounded
up or down – the choice of which will depend on the application.
Assuming we choose in this case the value 46 for pdt, this gives
a value of t_pd, of 15 µs and an actual minimum pulse width of
1525·2µs = 9·8µs.
From Table 7, pdt = 46 corresponds to a value of PDT, the 7-
bit word in temporary register R0 of 1010010.
The data which must be programmed into the three tempo-
rary registers R0, R1 and R2 (for transter into the initialisation
register) in order to achieve the parameters in the example given,
is shown in Fig. 15.
Temporary Register R0
11010010
CR PDT₆ PDT₅ PDT₄ PDT₃ PDT₂ PDT₁ PDT₀
Temporary Register R1
1 0 0XX 0 1 0
FRS₂ FRS₁ FRS₀ X X CFS₂ CFS₂ CFS₂
Temporary Register R2
XX 1 1 0 0 0 0
X X PDY₅ PDY₄ PDY₃ PDY₂ PDY₁ PDY₀
Fig. 15