MA828 Datasheet, PDF (6/16 Pages) List of Unclassifed Manufacturers – THREE-PHASE PULSE WIDTH MODULATION WAVEFORM GENERATOR

MA828
The power frequency range is a function of the carrier
waveform frequency (f_CARR) and a multiplication factor m, de-
termined by the 3-bit FRS word. The value of m is determined
as shown in Table 5.
FRS word 110 101 100 011 010 001 000
Value of m 64 32 16 8 4 2 1
Table 5 Values of carrier frequency multiplicaion factor m
The power frequency range, f_RANGE, is then given by:
f_RANGE
=
f_CARR
384
3
m
where f_CARR = carrier frequency and m = 1, 2, 4, 8, 16, 32 or 64
(as set by CFS).
X X PDY₅ PDY₄ PDY₃ PDY₂ PDY₁ PDY₀
DON’T
CARE
PULSE
DELAY
SELECT WORD
PDY₅ = MSB
PDY₀ = LSB
Fig. 7 Temporary register R2
Pulse delay time
The pulse delay time affects all six PWM outputs by delaying
the rising edges of each of the outputs by an equal amount.
The pulse delay time is a function of the carrier waveform
frequency and pdy, defined by the 6-bit pulse delay time select
word (PDY). The value of pdy is selected as shown in Table 6.
PDY word
Value of pdy
111111 111110 ...etc...
1
2
...etc...
Table 6 Values of pdy
000000
64
The pulse delay time, t_pdy, is then given by:
t_pdy
=
pdy
f_CARR3512
where pdy = 1- 64 (as set by PDY) and f_CARR = carrier frequency.
Fig 8 shows the eftect of the pulse delay circuit.
It should be noted that as the pulse delay circuit follows the
pulse deletion circuit (see Fig. 2), the minimum pulse width seen
at the PWM outputs will be shorter than the pulse deletion time
set in the initialisation register. The actual shortest pulse generated
is given by t_pd 2t_pdy.
PWM SIGNAL
REQUIRED AT
INVERTER OUTPUT
tpdy
tpdy
OUTPUT SIGNAL TO
DRIVE TOP SWITCH
INVERTER ARM
OUTPUT SIGNAL TO
DRIVE BOTTOM SWITCH
INVERTER ARM
tpdy
tpdy
t_pdy = PULSE DELAY TIME
Fig. 8 Effect of pulse delay on PWM pulse train
CR PDT₆ PDT₅ PDT₄ PDT₃ PDT₂ PDT₁ PDT₀
COUNTER
RESET
PULSE DELETION
TIME
SELECT WORD
PDT₆ = MSB
PDT₀ = LSB
Fig. 9 Temporary register R0
Pulse deletion time
To eliminate short pulses the true PWM pulse train is passed
through a pulse deletion circuit. The pulse deletion circuit com-
pares pulse widths with the pulse deletion time set in the
initialisation register. lf a pulse (either positive or negative) is
greater than or equal in duration to the pulse deletion time, it is
passed through unaltered, otherwise the pulse is deleted.
The pulse deletion time, t_pd , is a function of the carrier wave
frequency and pdt, defined by the 7-bit pulse deletion time word
(PDT). The value of pdt is selected as shown in Table 7.
PDT word
Value of pdt
1111111 1111110 ...etc...
1
2
...etc...
Table 7 Values of pdt
0000000
128
The pulse deletion time, t_pd, is then given by:
pdt
t_pd = _fCARR3512
where pdt = 1-128 (as set by PDT) and f_CARR = carrier frequency.
Fig. 10 shows the effect of pulse deletion on a pure PWM
waveform.
Counter reset
When the CR bit is active (i.e., Iow) the internal power
frequency phase counter is set to 0 degrees for the red phase.
The power frequency is then set to 0Hz and cannot be
changed via the normal frequency control.
Control Register Function
This 24-bit register contains the parameters that would
normally be modified during PWM cycles in order to control
the operation of the motor.
The parameters set in the control register are as follows:
Power frequency (speed)
Allows the power frequency of the PWM outputs to be
adjusted within the range specified in the initialisation register
Forward/reverse
Allows the direction of rotation of the AC motor to be
changed by changing the phase sequence of the PWM
outputs.
Power frequency amplitude
By altering the widths of the PWM output pulses while
maintaining their relative widths, the amplitude of the power
waveform is effectively altered whilst maintaining the same
power frequency.
Overmodulation
Allows the output waveform amplitude to be doubled so
that a quasi-squarewave is produced. A combination of
overmodulation and a lower power frequency can be used to
achieve rapid braking in AC motors.
Output inhibit
Allows the outputs to be set to the low state while the PWM
generation continues internally. Useful for temporarily inhib-
iting the outputs without having to to change other register
contents.
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