COM20051 Datasheet, PDF (78/82 Pages) List of Unclassifed Manufacturers – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

TXEN
t1
nPULSE1
nPULSE2
(Internal Clk)
t9
t4
t3
t2
t5
t6
t7
RXIN
t10
t11
t8
LAST BIT
(400 nS BIT TIME)
Parameter
t1 nPULSE2 High to TXEN Low
t2 nPULSE1 Pulse Width
t3 nPULSE1 Period
t4 nPULSE2 Low to nPULSE1 Low
t5 nPULSE2 High Time
t6 nPULSE2 Low Time
t7 nPULSE2 Period
t8 nPULSE2 High to TXEN High
t9 (first rising edge on nPULSE2 after Last Bit Time)
TXEN Low to First nPULSE1 Low**
t10 RXIN Pulse Width
t11 RXIN Period
min typ max units
0
50 nS
200*
nS
400*
nS
0
50 nS
100*
nS
100*
nS
200*
nS
0
50 nS
650
750 nS
10 200*
nS
400*
nS
* t5,t6 = 2 x (crystal period) for clock frequencies other than 20 MHz.
* t2,t7,t10 = 4 x (crystal period) for clock frequencies other than 20 MHz.
* t3,t11 = 8 x (crystal period) for clock frequencies other than 20 MHz.
** t9: For clock frequencies other than 20 MHz, t9 = 14 x (clock period) ± 50 nsec.
This period applies to data of two consecutive one's.
Note: Clock frequency for 5 Mbps is 40 MHz.
FIGURE 28 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING
(These signals are to and from the differential driver or the cable)
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