COM20051 Datasheet, PDF (43/82 Pages) List of Unclassifed Manufacturers – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

at any given time. The commands may be
given in any order.
• Up to two outstanding transmit interrupts
and two outstanding receive interrupts are
stored by the device, along with their
respective status bits.
• The Interrupt Mask bits act on TTA (Rising
Transition on Transmitter Available) for
transmit operations and TRI (Rising
Transition of Receiver Inhibited) for receive
operations. TTA is set upon completion of a
packet transmission only. TRI is set upon
completion of a packet reception only.
Typically there is no need to mask the TTA
and TRI bits after clearing the interrupt.
• The traditional TA and RI bits are still
available to reflect the present status of the
device.
MSB
Transmit Command Chaining
When the microcontroller issues the first "Enable
Transmit to Page fnn" command, the ARCNET
core responds in the usual manner by resetting
the TA and TMA bits to prepare for the
transmission from the specified page. The TA bit
can be used to see if there is currently a
transmission pending, but the TA bit is really
meant to be used in the non-chaining mode only.
The TTA bits provide the relevant information for
the device in the Command Chaining mode.
In the Command Chaining Mode, at any time
after the first command is issued, the processor
can issue a second "Enable Transmit from Page
fnn" command. The ARCNET core stores the
fact that the second transmit command was
issued, along with the page number.
After the first transmission is completed, the
ARCNET core updates the Status Register by
setting the TTA bit, which generates an interrupt.
The interrupt service routine should read the
Status Register. At this point, the TTA bit will be
found to be a logic "1" and the TMA (Transmit
Message Acknowledge) bit will tell the processor
whether the transmission was successful. After
reading the Status Register, the "Clear Transmit
Interrupt"
LSB
TRI
RI
TA
POR
TEST
RECON
TMA
TTA
TRI
TMA
TTA
FIGURE 12 – COMMAND CHAINING STATUS REGISTER QUEUE
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