COM20051 Datasheet, PDF (28/82 Pages) List of Unclassifed Manufacturers – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

Data Register (Location +04Hex)
This read/write 8-bit register is used as the
channel through which the data to and from the
RAM passes. The data is placed in or retrieved
from the address location presently specified by
the address pointer. The contents of the Data
Register are undefined upon hardware reset. In
the case of READ operation, the Data Register is
loaded with the contents of ARCNET Core
Internal RAM upon writing Address Pointer Low-
only once.
Tentative ID Register (Location +07Hex)
microsequencer of the ARCNET core does not
wake up until a Node ID other than zero is
written into the Node ID Register. During this
time, no microcode is executed, no tokens are
passed by this node, and no reconfigurations are
caused by this node. Once a non-zero Node ID
is placed into the Node ID Register, the core
wakes up but will not join the network until the
TXEN bit of the Configuration Register is set.
While the Transmitter is disabled, the Receiver
portion of the device is still functional and will
provide the user with useful information about
the network. The Node ID Register defaults to
the value 0000 0000 upon hardware reset only.
The Tentative ID Register is a read/write 8-bit Next ID Register (Location +07Hex)
register accessed when the Sub Address Bits
are set up accordingly (please refer to the
The Next ID Register is an 8-bit, read-only
Configuration Register description). The register, accessed when the sub-address bits are
Tentative ID Register can be used while the set up accordingly (please refer to the
node is on-line to build a network map of those
nodes existing on the network. It minimizes the
Configuration Register). The Next ID Register
holds the value of the Node ID to which the
need for operator interaction with the network. COM20051 will pass the token. When used in
The node determines the existence of other
nodes by placing a Node ID value in the
conjunction with the Tentative ID Register, the
Next ID Register can provide a complete network
Tentative ID Register and waiting to see if the map. The Next ID Register is updated each time
Tentative ID bit of the Diagnostic Status Register a node enters/leaves the network or when a
gets set. The network maps developed by this
method has only historical value, since nodes
network reconfiguration occurs. Each time the
microsequencer updates the Next ID Register, a
may join or depart from the network at any time. New Next ID interrupt is generated. This bit is
When using the Tentative ID feature, a node
cannot detect the existence of the next logical
cleared by reading the Next ID Register. Default
value is 0000 0000 upon hardware or software
node to which it passes the token. The Next ID reset.
Register will hold the ID value of that node. The
Tentative ID Register defaults to the value 0000
Status Register (Location +00Hex)
0000 upon hardware reset only.
The ARCNET Status Register is an 8-bit read-
Node ID Register (Location +07Hex)
only register. All of the bits, except for bits 5 and
6, are software compatible with previous SMSC
The Node ID Register is a read/write 8-bit ARCNET devices. In previous SMSC ARCNET
register accessed when the Sub Address Bits
are set up accordingly (please refer to the
devices the Extended Timeout status was
provided in bits 5 and 6 of the Status Register.
Configuration Register). The Node ID Register
contains the unique value which identifies this
In the COM20020, the COM20020-5,
COM20010, COM90C66, and the COM90C165,
particular node. Each node on the network must
occupy a unique Node ID value at all times. The
these bits exist in and are controlled by the
Configuration Register. The Status Register
Duplicate ID bit of the Diagnostic Status Register
helps the user find a unique Node ID. Refer to
contents are defined as in Table 6, but are
defined differently during the Command
the Initialization Sequence section for further Chaining operation. Please refer to the
detail on the use of the DUPID bit. The Command Chaining section for the definition of
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