NUC910ABN Datasheet, PDF (423/669 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC910ABN
32-BIT ARM926EJ-S BASED MCU
Control and Status Register (CSR)
Register
CSR
Offset
0xB000_A000
R/W Description
R/W Control and Status Register
Reset Value
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
HI_FREQ ATA_EN RESETn SW_RST
Bits
[3]
[2]
[1]
[0]
Descriptions
HI_FREQ
ATA_EN
RESETn
SW_RST
Engine Clock is in High Frequency
This bit will effect some engine core logics, software should set this bit
exactly match the actual engine clock which been used.
0 = Engine clock is 33MHz.
1 = Engine clock is 66MHz.
Hardware ATAPI Mode Enable
0 = Disable ATAPI core.
1 = Enable ATAPI core.
Device Hardware Reset
0 = The RESET- pin is negated (in HIGH level).
1 = The RESET- pin is asserted (in LOW level).
NOTE: Software should control this bit to generate a waveform like HIGH ->
LOW -> HIGH, and according to ATAPI-6 specification, the LOW period
should be at least 2ms.
Software Engine Reset
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit will reset the internal state machine and counters
(include DMACSR[DMAen], DMACSR[UDMAen] and DMACSR[EOSS]). The
contents of control register will not be cleared. This bit will auto clear after
few clock cycles.
Publication Release Date: Jun. 18, 2010
423
Revision: A4