NUC910ABN Datasheet, PDF (273/669 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC910ABN
32-BIT ARM926EJ-S BASED MCU
7.9 DMA Controller (DMAC)
The DMA Controller provides a DMA (Direct Memory Access) function for ATAPI and FMI to exchange data
between system memory (ex. SDRAM) and shared buffer (one 2048 bytes). Arbitration of DMA request
between ATAPI and FMI is done by DMAC’s bus master (Priority: ATAPI > FMI). Software just simply fills in
the starting address and enables DMAC, and then you can let DMAC to handle the data transfer
automatically.
There is one 2048 bytes shared buffer inside DMAC, separate into four 512 bytes ping-pong FIFO. It can
provide multi-block transfers using ping-pong mechanism for ATAPI and FMI. Software can access these
shared buffers directly when ATAPI and FMI are not in busy.
Features:
 Support single DMA channel
 Support hardware Scatter-Getter function
 One 2048 bytes shared buffer is embedded
 Automatic arbitration of DMA request for ATAPI and FMI
7.9.1 DMA Controller Registers Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W Description
Shared Buffer
FB_0
……
FB_511
0XB000_C000
……
0xB000_C7FC
DMAC Registers
DMACCSR
0xB000_C800
DMACSAR1 0xB000_C804
DMACSAR2 0xB000_C808
DMACBCR
0xB000_C80C
DMACIER
0xB000_C810
DMACISR
0xB000_C814
R/W Shared Buffer (FIFO)
R/W
R/W
R/W
R
R/W
R/W
DMAC Control and Status Register
DMAC Transfer Starting Address Register 1
DMAC Transfer Starting Address Register 2
DMAC Transfer Byte Count Register
DMAC Interrupt Enable Register
DMAC Interrupt Status Register
Reset Value
N/A
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0001
0x0000_0000
Publication Release Date: Jun. 18, 2010
273
Revision: A4