NUC910ABN Datasheet, PDF (184/669 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC910ABN
32-BIT ARM926EJ-S BASED MCU
Bits
[0]
Descriptions
RunStop
Run/Stop (R/W)
1=Run. 0=Stop. When set to a 1, the Host Controller proceeds with
execution of the schedule. The Host Controller continues execution as long as
this bit is set to a 1. When this bit is set to 0, the Host Controller completes
the current and any actively pipelined transactions on the USB and then
halts. The Host Controller must halt within 16 micro-frames after software
clears the Run bit. The HC Halted bit in the status register indicates when the
Host Controller has finished its pending pipelined transactions and has
entered the stopped state. Software must not write a one to this field unless
the host controller is in the Halted state (i.e. HCHalted in the USBSTS
register is a one). Doing so will yield undefined results.
USB Status Register (USTSR)
Register
Address
R/W Description
Reset Value
USTSR ^0xB000_5024
R/W USB Status Register
0x0000_1000
31
30
23
22
15
ASSTS
14
PSSTS
7
6
Reserved
29
21
13
RECLA
5
IntAsynA
28
27
Reserved
20
19
Reserved
12
11
HCHalted
4
HSERR
3
FLROVER
26
25
18
17
10
9
Reserved
2
1
PortCHG ^UERRINT
24
16
8
0
USBINT
Bits
[15]
Descriptions
ASSTS
Asynchronous Schedule Status (RO)
The bit reports the current real status of the Asynchronous Schedule. If this
bit is a zero then the status of them Asynchronous Schedule is disabled. If
this bit is a one then the status of the Asynchronous Schedule is enabled.
The Host Controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous
Schedule Enable bit in the USBCMD register. When this bit and the
Asynchronous Schedule Enable bit are the same value, the Asynchronous
Schedule is either r enabled (1) or disabled (0).
Publication Release Date: Jun. 18, 2010
184
Revision: A4