NUC910ABN Datasheet, PDF (280/669 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC910ABN
32-BIT ARM926EJ-S BASED MCU
DMAC Interrupt Status Register (DMACISR)
Register
DMACISR
Offset
R/W
0xB000_C814 R/W
Description
DMAC Interrupt Status Register
Reset Value
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
WEOT_IF TABORT_IF
Bits
[1]
Descriptions
WEOT_IF
Wrong EOT Encountered Interrupt Flag
When DMA Scatter-Getter function is enabled, and EOT of the descriptor is
encountered before DMA transfer finished (that means the total sector count
of all PAD is less than the sector count of ATAPI or FMI), this bit will be set.
0 = No EOT encountered before DMA transfer finished.
1 = EOT encountered before DMA transfer finished.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.
DMA Read/Write Target Abort Interrupt Flag
0 = No bus ERROR response received.
[0]
TABORT_IF
1 = Bus ERROR response received.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.
NOTE: When DMAC’s bus master received ERROR response, it means that target abort is happened.
DMAC will stop transfer and respond this event to software, ATAPI and FMI; then go to IDLE state. When
target abort occurred or WEOT_IF is set, suggest software reset DMAC and IP, and then transfer those
data again.
Publication Release Date: Jun. 18, 2010
280
Revision: A4