SD1010A Datasheet, PDF (39/45 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010A
0: disable detection
1: detect MAX/MIN using R color
2: detect MAX/MIN using G color
3: detect MAX/MIN using B color
Agc_en
1 RW 5DH[0] Automatic gain control enable
Agc_gain_red
8 RW 5EH Gain amount for R color
Agc_gain_green
8 RW 5FH Gain amount for G color
Agc_gain_blue
8 RW 60H Gain amount for B color
Agc_offset_red
8 RW 61H Offset amount for R color
Agc_offset_green
8
RW 62H Offset amount for G color
Agc_offset_blue
8 RW 63H Offset amount for B color
Input_max
8
R 64H Detected maximum input data (please see 5DH)
Input_min
8
R 65H Detected minimum input data (please see 5DH)
ICS_freq_state
1 RW 66H[5] Forces auto calibration to calculate the hsize value for a
particular clock frequency when supplied by ics chips
ICS_hsize_valid
1 RW 66H[4] Indicates when hsize value is ready for cpu to read in
ics mode. Can be clear by cpu
ICS_iq_valid
1 RW 66H[3] Indicates when image quality is ready for cpu to read in
ics mode. Can be clear by cpu
IQ_valid
1 RW 66H[2] Indicates when image quality is ready for cpu to read in
Regular non-ics mode. Can be clear by cpu
Divisor_valid
1 RW 66H[1] Indicates when auto clock frequency calibration is done
and frequency value is ready for cpu to read. Can be
clear by cpu
Non_full_screen
1 RW 66H[0] Indicates when input data is non full screen. Can be
clear by cpu
Divisor_value
11
R 67H[2:0], Read only register containing value of clock frequency
68H when divisor_valid is asserted
IQ_value
30
R 69H[5:0], Read only register containing value of image quality
6AH,6BH, when either ics_iq_valid or iq_valid is asserted
6CH
Panel_on
1 RW 6DH[0] 1: turn on all the outputs to the panel
0: disable outputs to the panel (need to disable
EEPROM 265H[3], 266H[7], 266H[3], 267H[7],
267H[3] to get complete output disable).
ICS_hsize_value 11
R 6EH[2:0], Read only register containing value of hsize when
6FH ics_hsize_valid is asserted
Rom_clk_sel
6 RW 70H[5:0] Divisor value use to divide fast pwm_free_clk to
slower free_clk
3.7. Control Flow
When SD1010A is powered up, the reference system and SD1010A will perform the
following functions in sequence:
1. System will generate a Power-On Reset to SD1010A.
2. Once the SD1010A receives the Reset, SD1010A will load the contents of
EEPROM and start the auto-calibration process.
November, 1999
SmartASIC Confidential
39
Revision B