SD1010A Datasheet, PDF (14/45 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010A
3.1.2.
Input mode detection and frequency detection
The SD1010A can automatically detect the mode of the input signal without any user
adjustment or driver running on the PC host or external CPU. This block
automatically detects polarity of input synchronization and the sizes of back porch,
valid data window and the synchronization pulse width in both vertical and horizontal
directions. The size information is then used not only to decide the input resolution, to
generate the frequency divider for the input PLL, to lock the PLL output clock with
HSYNC, but also to automatically scale the image to full screen and to synchronize
the output signal with the input signal.
The detection logic is always active to automatically detect any changes to the input
mode. Users can manually change the input mode information at run time through the
CPU interface. Detailed operation of the CPU interface is described in Section 3.6.
“CPU Interface”.
Mode detection and frequency detection can be independently turned ON or OFF by
the external CPU. This feature allows system customers to have better control of the
mode-detection and frequency detection process. When the detection is turned OFF,
the external CPU can change the input mode and frequency definitions.
3.1.3.
Phase calibration
The SD1010A can automatically calibrate the phase of the sample clock in order to
preserve the bandwidth of the input signal and to get the best quality. The SD1010A
implements a proprietary image quality function. During the auto-calibration process,
the SD1010A continues to search for the best phase to optimize the image quality.
The output image may display some jitter and blurring during the auto-calibration
process, and the image will become crisp and sharp once the optimum phase is found.
User can change the sampling clock phase value through the external CPU. Detailed
operation of the CPU interface is described in Section 3.6. “CPU Interface”.
The phase calibration process can be delayed and even disabled by the external CPU
if the system designer wants to have his/her own implementation. The phase
calibration can be independently turned ON or OFF by the external CPU. When the
calibration is turned OFF, the external CPU can change the input mode and frequency
definitions.
3.1.4.
PWM operation
The SD1010A implements a unique algorithm to adjust the phase of the A/D
converter’s sampling clock. An external delay circuit is required to compliment the
SD1010A for the phase-calibration process. The SD1010A generates a Pulse-Width
Modulated (PWM) signal to the external delay circuit. The delay circuit should insert
a certain amount of time delay synchronization pulse based upon the width of the
PWM signal. A brief circuit diagram for the PWM is shown in Figure 3.
November, 1999
SmartASIC Confidential
14
Revision B