MB8117800A-60 Datasheet, PDF (23/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM

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MB8117800A-60/-70
VIH
RAS _VIL
VIH
CAS
VIL
VIH
A0 to A10 _VIL
VIH
WE
VIL
DQ ^VIH
(Input) VIL
DQ ^VOH
(Output) VOL
VIH
OE
VIL
Fig. 16 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRCD
tCP
tFRSH
tRP
tCRP
tFCAS
tASC
tRCS
tFCAH
COLUMN ADDRESSES
tFCWD
tCWL
tRWL
tDZC
tWP
tDS
tDH
HIGH-Z
tOED
tFCAC
VALID DATA IN
HIGH-Z
tDZO
tON
tOEA
tOEZ
HIGH-Z
tOEH
“H” or “L”
Valid Data
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function
of CAS-before-RAS refresh circuitry. If, a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is
held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A0 through A10 are defined by the on-chip refresh counter.
Column Address: Bits A0 through A9 are defined by latching levels on A0-A9 at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows ;
1) Initialize the internal refresh address counter by using 8 RAS-only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 2048 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-
before-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 2048 times with addresses
generated by the internal refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 2048 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
(At recommended operating conditions unless otherwise noted.)
No.
Parameter
Symbol
MB817800A-60
Min.
Max.
MB817800A-70 _Unit
Min.
Max.
90 Access Time from CAS
tFCAC
—
50
—
55
ns
91 Column Address Hold Time
tFCAH
35
—
35
—
ns
92 CAS to WE Delay Time
tFCWD
70
—
77
—
ns
93 CAS Pulse Width
94 RAS Hold Time
tFCAS
90
tFRSH
90
—
99
—
99
—
ns
—
ns
Note: Assumes that CAS-before-RAS refresh counter test cycle only.
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