MB8117800A-60 Datasheet, PDF (11/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM

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MB8117800A-60/-70
Notes: *1. Referenced to VSS.
*2. ICC depends on the output load conditions and cycle rates; The specified values are obtained with the
output open. ICC depends on the number of address change as RAS = VIL, CAS = VIH and VIL > –0.3 V.
ICC1, ICC3, ICC4 and ICC5 are specified at one time of address change during RAS = VIL and CAS = VIH. ICC2
is specified during RAS = VIH and VIL > –0.3 V.
*3. An initial pause (RAS = CAS = VIH) of 200 µs is required after power-up followed by any eight RAS-only cycles
before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight
CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
*4. AC characteristics assume tT = 5 ns.
*5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also transition times are
measured between VIH (min) and VIL (max).
*6. Assumes that tRCD ≤ tRCD (max), tRAD ≤ tRAD (max). If tRCD is greater than the maximum recommended value
shown in this table, tRAC will be increased by the amount that tRCD exceeds the value shown. Refer to Fig.2 and 3.
*7. If tRCD ≥ tRCD (max), tRAD ≥ tRAD (max), and tASC ≥ tAA – tCAC – tT, access time is tCAC.
*8. If tRAD ≥ tRAD (max) and tASC ≤ tAA – tCAC – tT, access time is tAA.
*9. Measured with a load equivalent to two TTL loads and 100 pF.
*10. tOFF and tOEZ is specified that output buffer change to high impedance state.
*11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled
exclusively by tCAC or tAA.
*12. tRCD (min) = tRAH (min) + 2 tT + tASC (min).
*13. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, access time is controlled
exclusively by tCAC or tAA.
*14. Either tRRH or tRCH must be satisfied for a read cycle.
*15. tWCS is specified as a reference point only. If tWCS ≥ tWCS (min) the data output pin will remain High-Z state
through entire cycle.
*16. Assumes that tWCS < tWCS (min).
*17. Either tDZC or tDZO must be satisfied.
*18. tCPA is access time from the selection of a new column address (that is caused by changing CAS from “L” to
“H”). Therefore, if tCP is long, tCPA is longer than tCPA (max).
*19. Assumes that CAS-before-RAS refresh.
*20. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristic only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and DOUT pin
will maintain high impedance state through-out the entire cycle. If tCWD ≥ tCWD (min), tRWD ≥ tRWD (min),
tAWD ≥ tAWD (min) and tCPWD ≥ tCPWD (min), the cycle is a read-modify-write cycle and data from the selected
cell will appear at the DOUT pin. If neither of the above conditions is satisfied, the cycle is a delayed write cycle
and invalid data will appear the DOUT pin, and write operation can be executed by satisfying tRWL, tCWL, and tRAL
specifications.
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