MB8117800A-60 Datasheet, PDF (17/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM

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MB8117800A-60/-70
Fig. 9 – FAST PAGE MODE READ CYCLE
VIH
RAS _VIL
tRAD
tCRP
VIH
CAS _VIL
tRCD
tCSH
tCAS
tASR
tRAH
A0 to A10 ^VIH
VIL
ROW
ADD
tAR
tASC
tCAH
COL
ADD
VIH
WE
VIL
DQ VIH
(Input) _VIL
DQ VOH
(Output) _VOL
VIH
OE
VIL
tRCS
tRCH
tDZC
tDZO
HIGH-Z
tOH
tCAC
tON
tRAC
HIGH-Z
tAA
tOEZ
tOEA
tRASP
tPC
tCP
tCAS
tASC
tCAH
COL
ADD
tRCS
tCPA
tDZC
tDZO tOH
tCAC
tON
tOFF
tAA
tOEA
tOED
tOH
tRHCP
tRSH
tCAS
tCAH
tASC
tRAL
COL
ADD
tRCH
tRCS tRCH
tDZC
tDZO
tOFF
tOEL
tCDD
HIGH-Z
tOEZ
tOED
tOH
tRP
tRRH
“H” or “ L”
Valid Data
DESCRIPTION
The fast page mode of operation permits faster sucessive memory operations at multiple column locations of the same row address.
This operations is performed by strobing in the row address and maintaining RAS at a Low level and WE at a Hight level druing all
successive memory cycles in which the row address is latched. The address time is determined by tCAC, tAA, tCPA, or tOEA, whichever
one is the latest in occurring.
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