MB8117800A-60 Datasheet, PDF (22/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM

MB8117800A-60/-70
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Fig. 15 – HIDDEN REFRESH CYCLE
VIH
RAS
VIL
VIH
CAS
VIL
A0 to A10 ^VIH
VIL
VIH
WE
VIL
DQ ^VIH
(Input) VIL
DQ ^VOH
(Output) VOL
VIH
OE
VIL
tRC
tRAS
tRP
tOEL
tRCD
tRAD
tRSH
tASR
tRAH
tASC
tAR
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tRCS
tRRH
tRC
tRAS
tCHR
tRP
tCRP
tDZC
tAA
tRAC
tCAC
tON
HIGH-Z
tDZO
tOEA
HIGH-Z
tCDD
tOFF
tOH
VALID DATA OUT
tOEZ
tOED
“H” or “L”
DESCRIPTION
A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of CAS
and cycling RAS. The refresh row address is provided by the on-chip refresh address counter. This eliminates the need for the ex-
ternal row address that is required by DRAMs that do not have CAS-before-RAS refresh capability.
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