SI5013 Datasheet, PDF (19/24 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5013
Pin #
7
8
9
10
11,14,18,21,
25
12
13
15
16
17
19
Table 8. Si5013 Pin Descriptions (Continued)
Pin Name
LOL
LTR
LOS
DSQLCH
VDD
DIN+
DIN–
GND
DOUT–
DOUT+
RESET/CAL
I/O Signal Level
Description
O
LVTTL Loss-of-Lock.
This output is driven low when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 9. If no exter-
nal reference is supplied, this signal will be active
when the internal PLL is no longer locked to the
incoming data.
I
LVTTL Lock-to-Reference.
When this pin is low, the DSPLL disregards the data
inputs. If an external reference is supplied, the out-
put clock locks to the supplied reference. If no
external reference is used, the DSPLL locks the
control loop until LTR is released.
Note: This input has a weak internal pullup.
O
LVTTL Loss-of-Signal.
This output pin is driven low when the input signal is
below the threshold set via LOS_LVL. (LOS opera-
tion is guaranteed only when ac coupling is used on
the DIN inputs.)
LVTTL Data Squelch.
When driven high, this pin forces the data present
on DOUT+ to zero and DOUT– to one. For normal
operation, this pin should be low. DSQLCH may be
used during LOS/LOL conditions to prevent random
data from being presented to the system.
Note: This input has a weak internal pulldown.
3.3 V
Supply Voltage.
Nominally 3.3 V.
I
See Table 2 Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins. AC coupling is recom-
mended.
GND
Production Test Input.
This pin is used during production testing and must
be tied to GND for normal operation.
O
CML
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
I
LVTTL Reset/Calibrate.
Driving this input high for at least 1 Ps will reset
internal device circuitry. A high to low transition on
this pin will force a DSPLL calibration. For normal
operation, drive this pin low.
Note: This input has a weak internal pulldown.
Rev. 1.4
19